Hello Michael,

Section 4.10.3 which you referenced above later includes the following paragraph:

A processor may or may not implement any of the paging-structure caches. Software should rely on neither their presence nor their absence. The processor may invalidate entries in these caches at any time. Because the processor may create the cache entries at the time of translation and not update them following subsequent modifications to the paging structures in memory, software should take care to invalidate the cache entries appropriately when causing such modifications. The invalidation of

TLBs and the paging-structure caches is described in Section 4.10.4.

The SDM is intended for software developers, and so it is phrased to aid in writing of safe and portable code, and to avoid making excessive assumptions about HW that may not hold for other processor designs of the same family or different family.

What is the problem you are trying to resolve with this information? Perhaps I can find out or refer you to more useful information or sources.

-Hussam

Hi Michael,

Could you find an answer to your question? I am also curious about this, whether page directory or table entries being end up in caches. There is some information about paging-structure caches but it's not clear how much can be cached there and there are no specific details on processors, i.e. Nehalem or Sandy Bridge.

Thanks for an update!