Hi,
could someone tell me where could i find a link to some results of performance of the cache testing, like wait state, latency, depending in case of hit ans miss?

I would like to know also, what is the policu of replacement in the 3 caches?
also is there write buffer in the gulftown? if yes what is its size? latency? line size or bloc size? dual or simple port, fifo or DPRAM?

And my last question is about the link below which gives me the ways for evaluating the latency of for example the L3 cache: one is in nanoiseconds and the others one is in number of cycle. What is the relationship betwwen nanos and number of clock cycle?

http://www.imp.polymtl.ca/horde/util/go.php?url=http%3A%2F%2Fwww.xbitlab...

Thank u thank u thank u for any answer