Improving the performance software applications is a constant challenge for software developers in the financial services industry. This webinar provides an overview of how to accelerate these computations, especially Monte Carlo and Black-Scholes, using a combination of the new Intel® Xeon Phi™ coprocessor and the Intel® Parallel Studio XE suite of software development tools. Areas explored include performance analysis, threading, vectorization, math library usage and compiler optimization.
BACKGROUND: A QUICK REFRESHER ON IDLE STATES
Warning: The following documents a control flag users may experiment with; however, it's not an official feature supported by the Intel® Xeon Phi™ Coprocessor.
I recently came across a post on the Intel® Many Integrated Core Architecture (Intel MIC Architecture) forum wherein the developer was expecting a certain count for a hardware event but this count was always zero. There are several cases in which you can encounter this behavior. Let’s walk through each scenario and take a closer look at what could be happening during the hardware event collection.