Download Program Optimization through Loop Vectorization [PDF 617KB]
In this white paper, we will use a very simplified finite difference stencil computation of the following form:
Gather-Scatter instructions may not be the optimal choice of instructions when you are trying to achieve superior performance on the Intel® Xeon Phi™ coprocessor. However, if your code uses indirect addressing or performs non-unit strided memory accesses, gather-scatter instructions may be the best option.
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This article describes the new features in the Intel® Math Kernel Library Sparse Matrix Vector Multiply Format Prototype Package (Intel® MKL SpMV Format Prototype Package) for use on the Intel® Xeon Phi™ coprocessor. The package includes a new two-stage API for select SpMV operations as well as support for the ELLPACK Sparse Block (ESB) format.
Sample Project: CPU Features Check(ZIP 1MB)
To squeeze the most performance out of the native part of your application, it could be important to distinguish between different CPU architectures. The separation makes sense for the compiler parameters and for certain parts of the source code, like for optimized assembly instructions.