• The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference.
• Haswell (2013) new instructionsare in theprogrammer's reference manual.
• In appendix C of the Intel 64 and IA-32 Architectures Optimization Reference Manual (available here), the latencies and throughput of instructions are listed.

Hi everybody,

I'd like to hear from Intel engineers that Latency of a General purpose MOV instruction on any Intel CPUs is 1 clock cycle. For example, I've completed a set of tests for Intel(R) Pentium(R) 4 CPU 1.60GHz and my numbers are as follows:

[ Intel C++ compiler - DEBUG ]
...
Overhead of Assignment: 1.091 clock cycles
...

Hi, 

I have some code where at some point, after doing SSE3 computations with __m128d-typed values, I need to:

a) store a __m128d value into one of the two halves of a __m256d value (not cast it!)

b) paste two __m128d values side-by-side into a __m256d value 

Are there any AVX intrinsics to perform these operations? 

Thanks in advance, 

Nick

Hi, 

I am a grad student in EE. I am looking for 8088/8086 core for my project. Project is to design a bus monitor which can interface with either 8088/8086. I searched on opencore.org but could not find. I am looking for one which has all pins exposed - ALE, RD, WR, DEN, Addr/Data etc. 

Please can someone point me in the right direction. 

Regards, 

Sandy