Analyze Pipeline Flush Losses on 64-Bit Intel Architecture

Submit New Article

February 28, 2009 11:00 PM PST


Challenge

Determine the causes of cycles lost due to pipeline flushes, based on events accumulated by the BE_Flush_Bubble counter. These stalled cycles are comprised of the following:

  • Branch mispredicts
  • Exceptions

 

Solution

Use the Intel® VTune™ Performance Analyzer to analyze the subevents BE_Flush_Bubble.xpn or BE_Flush_Bubble.bru to find out directly if a stall was a branch mispredict or an exception.

The following table lists all the subevents for the BE_Flush_Bubble counter.

Extension

PMC.umask

Description

ALL

bxx00

Back-end was stalled due to either an exception/interruption or branch-misprediction flush.

BRU

bxx01

Back-end was stalled due to a branch-misprediction flush.

XPN

bxx10

Back-end was stalled due to an exception/interruption flush.

---

bxx11

(* nothing will be counted *)

 

In general, the most effective way to deal with significant loss of throughput due to pipeline flushes is to compile using profile-guided feedback and interprocedural inlining. See Chapter 9 of the manual Introduction to Microarchitectural Optimization for Itanium® Processors for an explanation of these concepts. To investigate the cause of lost cycles of this type, use occurrence events to show the details of the pipeline flushes.

Source

Introduction to Microarchitectural Optimization for Itanium® Processors