Block-Matching In Motion Estimation Algorithms

Introduction

The Streaming SIMD Extensions 2 (SSE2) technology introduces new Single Instruction Multiple Data (SIMD) double-precision floating-point instructions and new SIMD integer instructions into the IA-32 Intel® architecture. The double-precision SIMD instructions extend functionality in a manner analogous to the single-precision instructions introduced with the Streaming SIMD Extensions (SSE). The 128-bit SIMD integer extensions are a full superset of the 64-bit integer SIMD instructions, with additional instructions to support more integer data types, conversion between integer and floating-point data types, and efficient operations between the caches and system memory. These instructions provide a means to accelerate operations typical of:

3D graphics
real-time physics
spatial (3D) audio
video encoding/decoding
encryption
scientific application

This application note demonstrates specifically an application of the 128-bit integer SIMD instructions, and includes examples of code that exploit the SSE2 instructions.

As an example of the usage of the 128-bit version of the psadbs and paddw instructions, this application note gives details on coding a fast block-matching algorithm. This type of code is used in MPEG and MPEG2 encoders and accounts for approximately 40-70% of execution time of the encoders.

Code Samples