| Last Modified On : | May 6, 2008 8:31 PM PDT |
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A method of interconnecting PEs, controllers, and memory by making all visible to each other over a common, shared data path (a set of data, address, and control lines). Only one bus master can control the bus at any particular cycle, enforcing a sequential ordering to bus operations and giving rise to the possibility for contention. Busses can be split, between I/O and memory, or between groups of processors, to reduce contention by isolating local operations.
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Alex
Very grateful.