<?xml version="1.0" encoding="UTF-8"?>
<!-- Generated on Wed, 23 May 2012 12:47:35 -0700 -->
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom">
  <channel>
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      <title>Pardus Linux: Intel Debugger may fail to start</title>
      <description><![CDATA[ Due to a compatibility problem with the default .gdbinit startup script delivered with Pardus Linux* 2011.2, 64-bit, the Intel® IDB Debugger may fail to start. If the debugger (command line tool 'idbc' or GUI version 'idb') doesn't start correctly, you may add the command line option -nx to bypass the .gdbinit startup script as follows:<br /><br />Running the debugger GUI:<br />$ idb -nx<br /><br />Running the command line debugger:<br />$ idbc -nx<br /><br />This is a known limitation with the Intel® IDB Debugger for Linux* as part of the Intel® Composer XE 2011 Update 8 and will be solved with one of the next update releases of the Composer XE. <br /> ]]></description>
      <link>http://software.intel.com/en-us/articles/pardus-linux-intel-debugger-may-fail-to-start/</link>
      <pubDate>Wed, 04 Jan 2012 15:00:00 -0800</pubDate>
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      <title>Multithreaded debugging issues on Pardus Linux</title>
      <description><![CDATA[ Due to an issue with the default libthread library on Pardus Linux* version 2011.2, 64-bit, the debugger cannot detect which threading library is being used by the debuggee. <br />So when using OpenMP* thread commands<br /><br /> idb info &lt;option&gt; <br /><br />in a debugging session the Intel® IDB Debugger will not provide any OpenMP related thread information. Multithreading debugging however is not affected by this limitation, it's just an issue with displaying the thread info.<br /> ]]></description>
      <link>http://software.intel.com/en-us/articles/multithreaded-debugging-issues-on-pardus-linux/</link>
      <pubDate>Tue, 03 Jan 2012 15:00:00 -0800</pubDate>
      <comments>http://software.intel.com/en-us/articles/multithreaded-debugging-issues-on-pardus-linux/#comments</comments>
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      <title>Intel Architecture and Processor Identification With CPUID Model and Family Numbers</title>
      <description><![CDATA[ <p>This article is intended to aid software developers in understanding the "big picture" of Intel®'s recent architecture and processor releases. The <a href="http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html">"tick tock" model</a> adds predictability to <a href="http://www.intel.com/content/www/us/en/processors/public-roadmap-article.html">Intel®'s architecture roadmap</a>. However within each "tick" and "tock" architecture, multiple processors are launched to support the many diverse computing needs of consumers. While the general <a href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Instruction Set Architecture (ISA)</a> and feature set within a given architecture are identical, certain model specific variations occur, and are generally enumerated through CPUID interrogation<a href="http://software.intel.com#_ftn1">[1]</a>. The CPUID model number is a convenient way of anticipating the model specific functionality that is available at runtime and subsequently designing the architecture specific parts of software (nevertheless, at runtime, the feature bits in the CPUID should <i>always</i> be verified before use).</p>
<p>The information in the table below is composed from the <a href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html">"Intel® Processor Identification and the CPUID Instruction"</a> and the <a href="http://ark.intel.com/">official Intel® product information source</a>.</p>
<p>For identifying a particular processor, please use the <a href="http://www.intel.com/support/processors/tools/piu/sb/CS-014921.htm">Intel® Processor Identification Utility</a> for Microsoft® Windows<sup>TM</sup> operating systems or the <a href="http://www.intel.com/support/processors/tools/piu/sb/CS-015823.htm">bootable version</a> for other operating systems<a href="http://software.intel.com#_ftn2" name="_ftnref2">[2]</a>.</p>
<p> </p>
<p><b>Notes</b></p>
<ul>
<li>The -EP suffix denotes a Dual Processor, meaning this processor is designed to operate in a Dual Processor platform (but can still operate in a Single Processor platform). The -EX suffix denotes a Multi-Processor (MP), meaning this processor is designed to operate in a Multiprocessor platform, but can still operate in a Single or Dual processor platform configuration.</li>
<li>The Family number is an 8-bit number derived from the processor signature by adding the Extended Family number (bits 27:20) and the Family number (bits 11:8). See section 5.1.2.2 of the <a href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html">"Intel Processor Identification and the CPUID Instruction"</a>.</li>
<li>The Model number is an 8 bit number derived from the processor signature by shifting the Extended Model number (bits 19:16) 4 bits to the left and adding the Model number (bits 7:4) . See section 5.1.2.2 of the <a href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html">"Intel Processor Identification and the CPUID Instruction"</a>.</li>
</ul>
<b>
<p> </p>
<p><a href="http://software.intel.com#_mainline" name="_mainline" >Mainline Architectures and Processors</a></p>
<p><i>This table includes the mainline processors on 90nm and later process technology. Please read and understand these important <a href="http://software.intel.com#_disclaimers">disclaimers</a> prior to use.</i></p>

<div class="WordSection1">
<table width="812" cellpadding="0" cellspacing="0" border="0" class="MsoNormalTable" >
<tbody>
<tr >
<td width="75" >
<p align="center" class="MsoNormal" ><b><span >Process<br />Technology</span></b></p>
</td>
<td width="112" >
<p align="center" class="MsoNormal" ><b><span >Microarchitecture<br />Codename</span></b></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><b><span >Processor<br />Codename</span></b></p>
</td>
<td width="67" >
<p align="center" class="MsoNormal" ><b><span >Processor Signature</span></b></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><b><span >Family Number</span></b></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><b><span >Model Number</span></b></p>
</td>
<td width="148" >
<p align="center" class="MsoNormal" ><b><span >Intel® Brand <br />Name(s)</span></b></p>
</td>
<td width="182" >
<p align="center" class="MsoNormal" ><b><span >Intel® Brand <br />Processor Number</span></b></p>
</td>
</tr>
<tr >
<td width="75" >
<p class="MsoNormal" align="center" ><span >22 nm<o:p></o:p></span></p>
</td>
<td width="112" >
<p class="MsoNormal" align="center" ><span class="SpellE"><span >IvyBridge</span></span><span ><o:p></o:p></span></p>
</td>
<td width="103" >
<p class="MsoNormal" align="center" ><span class="SpellE"><span >IvyBridge</span></span><span ><o:p></o:p></span></p>
</td>
<td width="67" >
<p class="MsoNormal" align="center" ><span >0x306Ax<o:p></o:p></span></p>
</td>
<td width="60" rowspan="27" >
<p class="MsoNormal" align="center" ><span >0x06<o:p></o:p></span></p>
</td>
<td width="60" >
<p class="MsoNormal" align="center" ><span >0x3A<o:p></o:p></span></p>
</td>
<td width="161" >
<p class="MsoNormal"><span >Core™ i3<br /> Core™ i5<br /> Core™ i7<br /> Core™ i7 Extreme<br /> Xeon™ E3<o:p></o:p></span></p>
</td>
<td width="179" >
<p class="MsoNormal"><span >i3-31xx/32xx-T/U<br /> i5-3xxx-T/S/M/K/ME<br /> i7-3xxx-S/K/M/QM/LE/UE/QE<br /> i7-3920XM <br /> E3-12xxV2<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="75" rowspan="9" >
<p class="MsoNormal" align="center" ><span >32 nm</span></p>
</td>
<td width="112" rowspan="4" >
<p class="MsoNormal" align="center" ><span >SandyBridge</span></p>
</td>
<td width="103" >
<p class="MsoNormal" align="center" ><span >SandyBridge</span></p>
</td>
<td width="67" >
<p class="MsoNormal" align="center" ><span >0x206Ax</span></p>
</td>
<td width="60" >
<p class="MsoNormal" align="center" ><span >0x2A</span></p>
</td>
<td width="161" >
<p class="MsoNormal"><span >Core™ i3<br /> Core™ i5<br /> Core™ i7<br /> Core™ i7 Extreme<br /> Celeron™ Desktop<br /> Celeron™ Mobile<br /> Pentium™ Desktop<br /> Pentium™ Mobile<br /> Xeon™ E3</span></p>
</td>
<td width="179" >
<p class="MsoNormal"><span >i3-21xx/23xx-T/M/E/UE<br /> i5-23xx/24xx/25xx-T/S/M/K<br /> i7-2xxx-S/K/M/QM/LE/UE/QE<br /> i7-29xxXM <br /> G4xx, G5xx<br /> 8xx, B8xx<br /> 350, G6xx, G6xxT, G8xx<br /> 9xx, B9xx<br /> E3-12xx</span></p>
</td>
</tr>
<tr >
<td width="103" >
<p class="MsoNormal" align="center" ><span >SandyBridge-E<o:p></o:p></span></p>
</td>
<td width="67" rowspan="3" >
<p class="MsoNormal" align="center" ><span >0x206Dx<o:p></o:p></span></p>
</td>
<td width="60" rowspan="3" >
<p class="MsoNormal" align="center" ><span >0x2D<o:p></o:p></span></p>
</td>
<td width="161" >
<p class="MsoNormal"><span >Core™ i7<br /> Core™ i7 Extreme<o:p></o:p></span></p>
</td>
<td width="179" >
<p class="MsoNormal"><span >I7-3820/3930K<br /> i7-3960X<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="103" >
<p class="MsoNormal" align="center" ><span >SandyBridge-EN<o:p></o:p></span></p>
</td>
<td width="161" >
<p class="MsoNormal"><span >Xeon™ E5<o:p></o:p></span></p>
</td>
<td width="179" >
<p class="MsoNormal"><span >E5-24xx<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="103" >
<p class="MsoNormal" align="center" ><span >SandyBridge-EP<o:p></o:p></span></p>
</td>
<td width="161" >
<p class="MsoNormal"><span >Xeon™ E5<o:p></o:p></span></p>
</td>
<td width="179" >
<p class="MsoNormal"><span >E5-16xx, 26xx/L/W<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="112" rowspan="5" >
<p align="center" class="MsoNormal" ><span >Westmere</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Arrandale</span></p>
</td>
<td width="67" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x2065x</span></p>
</td>
<td width="60" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x25</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Celeron™ Mobile<br />Pentium™ Mobile<br />Core™ i3<br />Core™ i5<br />Core™ i7</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >P4xxx, U3xxx<br />P6xxx, U5xxx<br />i3-3xxE, i3-3xxM, i3-3xxUM<br />i5-4xxM/UM, i5-5xxE/M/UM<br />i7-6xxE/LE/UE/M/LM/UM</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Clarksdale</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Pentium™ Desktop<br />Core™ i3<br />Core™ i5<br />Xeon™ 3000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >G69xx<br />i3-5xx<br />i5-6xx, i5-6xxK<br />L34xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Gulftown</span></p>
</td>
<td width="67" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x206Cx</span></p>
</td>
<td width="60" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x2C</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ i7<br />Core™ i7 Extreme<br />Xeon™ 3000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >i7-9xx<br />i7-9xxX<br />W36xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Westmere-EP</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 3000<br />Xeon™ 5000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >W36xx<br />L56xx, E56xx, X56xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Westmere-EX</span></p>
</td>
<td width="67" >
<p align="center" class="MsoNormal" ><span >0x206Fx</span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x2F</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ E7</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >E7-2xxx, E7-48xx, E7-88xx</span></p>
</td>
</tr>
<tr >
<td width="75" rowspan="11" >
<p align="center" class="MsoNormal" ><span >45 nm</span></p>
</td>
<td width="112" rowspan="6" >
<p align="center" class="MsoNormal" ><span >Nehalem</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Clarksfield</span></p>
</td>
<td width="67" rowspan="3" >
<p align="center" class="MsoNormal" ><span >0x106Ex</span></p>
</td>
<td width="60" rowspan="3" >
<p align="center" class="MsoNormal" ><span >0x1E</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ i7<br />Core™ i7 Extreme</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >i7-7xxQM, i7-8xxQM<br />i7-9xxXM</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Lynnfield</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ i5<br />Core™ i7<br />Xeon™ 3000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >i5-7xx, i5-7xxS<br />i7-8xx, i7-8xxS, i7-8xxK<br />X34xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Jasper Forest</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 5000<br />Celeron™ Desktop</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >LC55xx, EC55xx<br />P10xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Bloomfield</span></p>
</td>
<td width="67" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x106Ax</span></p>
</td>
<td width="60" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x1A</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ i7 Extreme<br />Core™ i7<br />Xeon™ 3000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >i7-965/975<br />i7-9x0<br />W35xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Nehalem-EP</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 5000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >L55xx, E55xx, X55xx, W55xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Nehalem-EX</span></p>
</td>
<td width="67" >
<p align="center" class="MsoNormal" ><span >0x206Ex</span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x2E</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 7000<br />Xeon™ 6000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >L75xx, E75xx, X75xx<br />E65xx, X65xx</span></p>
</td>
</tr>
<tr >
<td width="112" rowspan="5" >
<p align="center" class="MsoNormal" ><span >Penryn</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Yorkfield</span></p>
</td>
<td width="67" rowspan="4" >
<p align="center" class="MsoNormal" ><span >0x1067x</span></p>
</td>
<td width="60" rowspan="4" >
<p align="center" class="MsoNormal" ><span >0x17</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ 2 Quad<br />Core™ 2 Extreme<br />Xeon™ 3000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >Q9xxx, Q8xxx, !9xxxS<br />QX9xxx<br />L33xx, <span class="baec5a81-e4d6-4674-97f3-e9220f0136c1" >X3350</span></span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Wolfdale</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Celeron™ Desktop<br />Core™ 2 Duo <br />Pentium™<br />Xeon™ 5000/3000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >E3xxx<br />E7xxx, E8xxx<br />E5xxx, E6xxx, E6xxxK<br />L52xx, E31xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Penryn</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ 2 Duo Mobile<br />Celeron™ M</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >P7xxx, P9xxx, SL9xxx<br />722</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Harpertown (DP)</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 5000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >L54xx, E54xx, X54xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Dunnington (MP)</span></p>
</td>
<td width="67" >
<p align="center" class="MsoNormal" ><span >0x106Dx</span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x1D</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 7000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >L74xx, E74xx, Q7xx</span></p>
</td>
</tr>
<tr >
<td width="75" rowspan="8" >
<p align="center" class="MsoNormal" ><span >65 nm</span></p>
</td>
<td width="112" rowspan="6" >
<p align="center" class="MsoNormal" ><span >Merom</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Clovertown</span></p>
</td>
<td width="67" rowspan="5" >
<p align="center" class="MsoNormal" ><span >0x006Fx</span></p>
</td>
<td width="60" rowspan="5" >
<p align="center" class="MsoNormal" ><span >0x0F</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 5000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >E53xx, L53xx, X53xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Kentsfield</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 3000<br />Core™ 2 Quad<br />Core™ 2 Extreme</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >X32xx<br />Q6600<br />QX6xxx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Conroe</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 3000<br clear="all"  />Pentium™<br />Core™ 2 Duo<br />Core™ 2 Extreme<br />Celeron™ Desktop</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >30xx<br />E21xx<br />E43xx,E6xxx<br /><span class="baec5a81-e4d6-4674-97f3-e9220f0136c1" >X6800</span><br />E1600</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Merom</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Core™ 2 Duo M<br />Pentium™ Mobile<br />Core™ 2 Extreme M</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >L7xxx,T5xxx,T7xxx,U7xxx<br />T3200<br />X7xxx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Woodcrest</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™ 5000</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >51xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Merom<br />Conroe</span></p>
</td>
<td width="67" >
<p align="center" class="MsoNormal" ><span >0x1066x</span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x16</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Celeron™ Desktop<br />Celeron™ Mobile</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >4xx<br />5xx</span></p>
</td>
</tr>
<tr >
<td width="112" rowspan="2" >
<p align="center" class="MsoNormal" ><span >Presler</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Cedar Mill</span></p>
</td>
<td width="67" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x0066x</span></p>
</td>
<td width="60" rowspan="4" >
<p align="center" class="MsoNormal" ><span >0x0F</span></p>
</td>
<td width="60" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x06</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Pentium™ 4</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >3xx, 6xx</span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Presler</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Pentium™ D</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >9xx</span></p>
</td>
</tr>
<tr >
<td width="75" rowspan="3" >
<p align="center" class="MsoNormal" ><span >90 nm</span></p>
</td>
<td width="112" rowspan="2" >
<p align="center" class="MsoNormal" ><span >Prescott</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Nocona<br />Irwindale</span></p>
</td>
<td width="67" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x0063x<br />0x0064x</span></p>
</td>
<td width="60" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x03/<br />0x04</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Xeon™</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span ></span></p>
</td>
</tr>
<tr >
<td width="106" >
<p align="center" class="MsoNormal" ><span >Prescott</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Celeron™ D<br />Pentium™ 4</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >3xx<br />5xx</span></p>
</td>
</tr>
<tr >
<td width="112" >
<p align="center" class="MsoNormal" ><span >Dothan</span></p>
</td>
<td width="106" >
<p align="center" class="MsoNormal" ><span >Dothan</span></p>
</td>
<td width="67" >
<p align="center" class="MsoNormal" ><span >0x006Dx</span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x06</span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x0D</span></p>
</td>
<td width="128" >
<p class="MsoNormal"><span >Celeron™ M<br />Pentium™ Mobile</span></p>
</td>
<td width="182" >
<p class="MsoNormal"><span >3xx<br />7xx</span></p>
</td>
</tr>
</tbody>
</table>
<p class="MsoNormal"> </p>
</div>
<p> </p>
<p><a name="_atom" href="http://software.intel.com#_atom" >Atom™ Architectures and Processors</a></p>
<p><i>This table includes the Atom™ processors on 45nm and later process technology. Please read and understand these important <a href="http://software.intel.com#_disclaimers">disclaimers</a> prior to use.</i></p>
<div class="WordSection1">
<table width="737" cellpadding="0" cellspacing="0" border="0" class="MsoNormalTable" >
<tbody>
<tr >
<td width="68" >
<p align="center" class="MsoNormal" ><b><span >Process<br />Technology<o:p></o:p></span></b></p>
</td>
<td width="76" >
<p align="center" class="MsoNormal" ><b><span >Architecture Codename<o:p></o:p></span></b></p>
</td>
<td width="75" >
<p align="center" class="MsoNormal" ><b><span >Processor Codename<o:p></o:p></span></b></p>
</td>
<td width="68" >
<p align="center" class="MsoNormal" ><b><span >Platform<br />Codename<o:p></o:p></span></b></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><b><span >Processor<br />Signature<o:p></o:p></span></b></p>
</td>
<td width="53" >
<p align="center" class="MsoNormal" ><b><span ><span ></span>Family<br />Number<o:p></o:p></span></b></p>
</td>
<td width="53" >
<p align="center" class="MsoNormal" ><b><span >Model <br />Number<o:p></o:p></span></b></p>
</td>
<td width="148" >
<p align="center" class="MsoNormal" ><b><span >Intel® Brand <br />Name(s)<o:p></o:p></span></b></p>
</td>
<td width="209" >
<p align="center" class="MsoNormal" ><b><span >Intel® Brand <br />Model Number<o:p></o:p></span></b></p>
</td>
</tr>
<tr >
<td width="68" >
<p align="center" class="MsoNormal" ><span >32 nm<o:p></o:p></span></p>
</td>
<td width="76" rowspan="4" >
<p align="center" class="MsoNormal" ><span >Atom™<o:p></o:p></span></p>
</td>
<td width="75" >
<p class="MsoNormal"><span class="SpellE"><span >Cedarview</span></span><span ><o:p></o:p></span></p>
</td>
<td width="68" >
<p class="MsoNormal"><span >Cedar Trail<o:p></o:p></span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x0366x<o:p></o:p></span></p>
</td>
<td width="53" rowspan="4" >
<p align="center" class="MsoNormal" ><span >0x06<o:p></o:p></span></p>
</td>
<td width="53" >
<p align="center" class="MsoNormal" ><span >0x36<o:p></o:p></span></p>
</td>
<td width="148" rowspan="4" >
<p align="center" class="MsoNormal" ><span >Atom™<o:p></o:p></span></p>
</td>
<td width="209" >
<p class="MsoNormal"><span >N2000 series:<span > </span>N26xx, N28xx<br />D2000 Series:<span > </span>D25xx (no HT), D27xx<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="68" rowspan="3" >
<p align="center" class="MsoNormal" ><span >45 nm<o:p></o:p></span></p>
</td>
<td width="75" >
<p class="MsoNormal"><span >Lincroft<o:p></o:p></span></p>
</td>
<td width="68" >
<p class="MsoNormal"><span >Oak Trail<o:p></o:p></span></p>
</td>
<td width="60" >
<p align="center" class="MsoNormal" ><span >0x0266x<o:p></o:p></span></p>
</td>
<td width="53" >
<p align="center" class="MsoNormal" ><span >0x26<o:p></o:p></span></p>
</td>
<td width="209" >
<p class="MsoNormal"><span >Z6xx (single core)<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="75" >
<p class="MsoNormal"><span class="SpellE"><span >Pineview</span></span><span ><o:p></o:p></span></p>
</td>
<td width="68" >
<p class="MsoNormal"><span >Pine Trail<o:p></o:p></span></p>
</td>
<td width="60" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x016Cx<o:p></o:p></span></p>
</td>
<td width="53" rowspan="2" >
<p align="center" class="MsoNormal" ><span >0x1C<o:p></o:p></span></p>
</td>
<td width="209" >
<p class="MsoNormal"><span >N4xx, D4xx (single core)<br />N5xx, D5xx (dual core)<o:p></o:p></span></p>
</td>
</tr>
<tr >
<td width="75" >
<p class="MsoNormal"><span >Silverthorne<o:p></o:p></span></p>
</td>
<td width="68" >
<p class="MsoNormal"><span >any<o:p></o:p></span></p>
</td>
<td width="209" >
<p class="MsoNormal"><span >Z5xx<o:p></o:p></span></p>
</td>
</tr>
</tbody>
</table>
<p class="MsoNormal"><o:p></o:p></p>
</div>
<p> </p>
<p><a href="http://software.intel.com#_disclaimers" name="_disclaimers" >Disclaimers</a></p>
<p class="Disclaimer"><b>Information in this article is intended as a convenient summary of the contents of the <a href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html">"Intel® Processor Identification and the CPUID Instruction"</a> application note and the <a href="http://ark.intel.com/">official Intel® product information source</a>. </b></p>
<p class="Disclaimer"><b>In <i>case of discrepancy,</i> the information in the <a href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html">original application note</a> and <a href="http://ark.intel.com/">product information source</a> supersede the contents of this article. (Please notify the author of any such discrepancy).</b></p>
<p class="Disclaimer"><b>Please consult <i><span >Section 2: Usage Guidelines</span></i> of the <a href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html">"Intel® Processor Identification and the CPUID Instruction"</a> for the proper use of CPUID.</b></p>
<p class="Disclaimer">Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See <a href="http://www.intel.com/products/processor_number">http://www.intel.com/products/processor_number</a> for details.</p>
<p class="Disclaimer"><br />All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.</p>
<hr align="left" size="1" width="33%" />
<p><a href="http://software.intel.com#_ftnref1" name="_ftn1"><br />[1]</a> For an example of interrogating CPUID to verify features please read <a href="http://software.intel.com/en-us/articles/using-cpuid-to-detect-the-presence-of-sse-41-and-sse-42-instruction-sets/">Using CPUID to Detect the presence of SSE 4.1 and SSE 4.2 Instruction Sets</a></p>
<p><a href="http://software.intel.com#_ftnref2" name="_ftn2">[2]</a> In Linux based operating systems you can type ‘cat /proc/cpuinfo' to obtain the processor family and model numbers (note they are formatted in decimal, while the tables in this article containhexadecimal formatting of these numbers).</p>
<p><b></b></p>
</b> ]]></description>
      <link>http://software.intel.com/en-us/articles/intel-processor-identification-with-cpuid-model-and-family-numbers/</link>
      <pubDate>Tue, 04 Oct 2011 00:00:00 -0700</pubDate>
      <comments>http://software.intel.com/en-us/articles/intel-processor-identification-with-cpuid-model-and-family-numbers/#comments</comments>
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      <category>Software Products General</category>
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      <category>Resources For Software Developers</category>
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    <item>
      <title>Intel Architecture Platform Terminology for Development Tools</title>
      <description><![CDATA[ <p>Intel® compilers and libraries support three platforms: general combinations of processor architecture and operating system type. This section explains the terms that Intel uses to describe the platforms in its documentation, installation procedures and support site.  <b>Note:</b> not all Intel software development tools support all three platforms.</p>
<p><b>IA-32 Architecture</b> refers to systems based on 32-bit processors generally compatible with the Intel Pentium® II processor, (for example, Intel® Pentium® 4 processor or Intel® Xeon® processor), or processors from other manufacturers supporting the same instruction set, running a 32-bit operating system.</p>
<p><b>Intel® 64 Architecture</b> (formerly Intel® EM64T)refers to systems based on IA-32 architecture processors which have 64-bit architectural extensions, (for example, Intel® Core™2 processor family), running a 64-bit operating system such as Microsoft Windows Vista* x64 or a Linux* "x86_64" variant. If the system is running a 32-bit  operating system, then IA-32 architecture applies instead. Systems based on AMD* processors running a 64-bit operating system are also supported by Intel compilers for Intel® 64 architecture applications.</p>
<p>64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.</p>
<p><b>IA-64 Architecture</b> refers to systems based on the Intel® Itanium® processor running a 64-bit operating system.</p> ]]></description>
      <link>http://software.intel.com/en-us/articles/intel-architecture-platform-terminology/</link>
      <pubDate>Tue, 10 Feb 2009 21:00:00 -0800</pubDate>
      <comments>http://software.intel.com/en-us/articles/intel-architecture-platform-terminology/#comments</comments>
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      <category>Software Products General</category>
      <category>Intel® C++ Compiler for Linux* Knowledge Base</category>
      <category>Intel® C++ Compiler for Windows* Knowledge Base</category>
      <category>Intel® Software Development Tool Suites for Intel® Atom™ Processor Knowledge Base</category>
      <category>Intel® Cluster Toolkit for Linux* Knowledge Base</category>
      <category>Intel® Cluster Toolkit for Windows* Knowledge Base</category>
      <category>Intel® Fortran Compiler for Linux* Knowledge Base</category>
      <category>Intel® Math Kernel Library Knowledge Base</category>
      <category>Intel® Parallel Amplifier Knowledge Base</category>
      <category>Intel® Parallel Composer Knowledge Base</category>
      <category>Intel® Parallel Inspector Knowledge Base</category>
      <category>Intel® Thread Checker for Windows* Knowledge Base</category>
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      <title>Processor and Compiler Compatibility in Intel MKL</title>
      <description><![CDATA[ <!--CTYPE html PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN" "http://www.w3.org/TR/REC-html40/loose.dt-->
<table cellpadding="0" cellspacing="15" border="0">
<tbody>
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<td class="bodycopy">
<p><b>System Requirements</b></p>
<p>Please refer to the <a href="http://software.intel.com/en-us/articles/intel-software-products-system-requirements/">Intel® Software Products System Requirements</a> in Intel® Math Kernel Library (Intel® MKL) release notes to find detailed or version-specific information about processor compatibility, compiler compatibility, and operating system requirements.</p>
<p><b>Processor Compatibility</b></p>
<p><b>Using the Intel MKL on Intel Processors</b><br />Intel MKL is optimized for the latest features and capabilities of Intel® processors (IA-32 and Intel® 64) supporting Intel® Streaming SIMD Extensions as well as Intel® Advanced Vector Extensions (Intel® AVX). The library automatically selects processor-optimized code at run time designed to provide optimal performance for that specific Intel processor.</p>
<p><b>Using the Intel MKL on non-Intel Processors</b><br />Intel MKL will run code that provides performance competitive with similar math libraries on AMD* processors using a variety of techniques which may include use of Streaming SIMD Extensions (SSE), SSE-2, and SSE-3 instruction sets and other architecture features compatible with Intel processors.</p>
<p><a name="2"></a><b>Compiler Compatibility</b></p>
<p>Refer the part of "Supported C/C++ and Fortran compilers" from <a target="_blank" href="http://software.intel.com/en-us/articles/intel-mkl-103-system-requirements/">Intel MKL release notes </a>for more details.  In addtion, the Intel MKL <a href="http://software.intel.com/en-us/articles/intel-mkl-link-line-advisor/">Link Line Advisor</a> can be particularly helpful for finding the right libraries to link.</p>
</td>
</tr>
</tbody>
</table>
<table cellpadding="0" cellspacing="0" border="0">
<tbody>
<tr>
<td></td>
</tr>
<tr>
<td height="10"></td>
</tr>
</tbody>
</table>
<p>
<table cellpadding="5" cellspacing="0" rules="none" border="1">
<tbody>
<tr>
<th align="left" valign="middle" >Optimization Notice</th>
</tr>
<tr bgcolor="#ccecff">
<td>
<p>Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.</p>
<p align="right">Notice revision #20110804</p>
</td>
</tr>
</tbody>
</table>
</p> ]]></description>
      <link>http://software.intel.com/en-us/articles/intel-math-kernel-library-intel-mkl-processor-and-compiler-compatibility/</link>
      <pubDate>Sun, 09 Nov 2008 00:00:00 -0800</pubDate>
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      <category>Software Products General</category>
      <category>Intel® Math Kernel Library Knowledge Base</category>
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    <item>
      <title>Intel® Math Kernel Library (Intel® MKL) - BLAS, CBLAS and LAPACK Compiling/Linking Functions &amp;Fortran and C/C++ Calls</title>
      <description><![CDATA[ <table border="0" cellpadding="0" cellspacing="15">
<tbody>
<tr>
<td class="bodycopy">
<p><b>Page Contents:</b></p>
<ul>
<li><a href="http://software.intel.com#1">Intel® Math Kernel Library use with C and Fortran languages. Calling LAPACK, BLAS, and CBLAS routines from C language environments.</a></li>
<li><a href="http://software.intel.com#3">How to Call BLAS Functions that Return the Complex Values in C/C++ Code</a></li>
<li><a href="http://software.intel.com#4">Example 1: Calling a Complex BLAS Level 1 Function from C</a></li>
<li><a href="http://software.intel.com#5">Example 2: Calling a Complex BLAS Level 1 Function from C++</a></li>
<li><a href="http://software.intel.com#6">Example 3: Using the CBLAS Interface Instead of Calling BLAS Directly from C Programs</a></li>
</ul>
<br /><a name="1"></a><b>Intel® Math Kernel Library use with C and Fortran languages. Calling LAPACK, BLAS, and CBLAS routines from C language environments.</b><br />The Intel Math Kernel Library is provided in C and Fortran environments. Not all of the Intel® MKL sub-libraries support both environments. In order to use these sub-libraries in both environments some "rules" need to be observed. <br /><br /> 
<table width="552" border="0" cellpadding="5" cellspacing="0">
<tbody>
<tr>
<td class="bodycopy" valign="top" align="left" bgcolor="#efefef"><b>LAPACK</b></td>
<td class="bodycopy" valign="top" align="left" bgcolor="#efefef">When calling LAPACK routines from C-language programs, make sure that you follow Fortran rules: Pass variables by 'address' as opposed to pass by 'value'. Be sure to store your data Fortran-style, i.e. data stored column-major rather than row-major order.</td>
</tr>
<tr>
<td class="bodycopy" valign="top" align="left"><b>BLAS</b></td>
<td class="bodycopy" valign="top" align="left">BLAS routines are Fortran-style routines. If you call BLAS routines from a C-language program you must follow the Fortran-style calling conventions: Pass variables by address as opposed to passing by value. Be sure to store data Fortran-style, i.e. data stored column-major rather than row-major order. We recommend that C and C++ programmers use the CBLAS interface to avoid simple mistakes when following these conventions. <br /></td>
</tr>
<tr>
<td class="bodycopy" valign="top" align="left" bgcolor="#efefef"><b>CBLAS</b></td>
<td class="bodycopy" valign="top" align="left" bgcolor="#efefef">CBLAS routines are provided as the C-style interface to the BLAS routines. Call CBLAS routines using regular C-style calls. When using the CBLAS interface, the header file mkl.h will simplify the programmer's development as it specifies enumerated values as well as prototypes of all the functions. The header determines if the program is being compiled with a C++ compiler, and if it is, the included file will be correct for use with C++ compilation.</td>
</tr>
<tr>
<td class="bodycopy" valign="top" align="left"><b>MKL.H</b></td>
<td class="bodycopy" valign="top" align="left">When using the CBLAS interface, the header file mkl.h will simplify the program development since it specifies enumerated values as well as prototypes of all the functions. The header determines if the program is being compiled with a C++ compiler, and if it is, the included file will be correct for use with C++ compilation.</td>
</tr>
</tbody>
</table>
<br /><br /><br /><a name="2"></a><b>How to Call BLAS Functions that Return the Complex Values in C/C++ Code</b><br />Calling complex BLAS function that return complex values from C must be handled carefully. The problem arises because these are Fortran functions, and the return values are handled quite differently for the two languages (C and Fortran) for complex values. While the Fortran language prohibits calling functions as subroutines, or vice versa, if you understand how a particular Fortran implementation returns function values you can make the appropriate call from C.  (The Fortran standard defines C interoperability features, but these are not used by Intel® MKL.)<br /><br />A Fortran function that returns a complex value returns its result in a variable passed as the first parameter in the calling sequence - a feature that can be exploited by the C programmer. <br /><br />The following example, for cdotc(), shows how this works. The function from Fortran is called as:
<blockquote>result = cdotc( n, x, 1, y, 1 )</blockquote>
From C this would look like: cdotc( &amp;result, &amp;n, x, &amp;one, y, &amp;one ) where the hidden parameter is exposed. <br /><br /><b>Note:</b> Intel® MKL has both upper case and lower case entry points in the BLAS so either all upper case or all lower case names are acceptable. <br /><br />Using this form the several level 1 BLAS functions that return complex values can be called from C, and thus, from C++. However, it is still easier to use the cblas interface. For instance, to call the same function using the cblas interface, the user would use:
<blockquote>cblas_cdotu( n, x, 1, y, 1, &amp;result )</blockquote>
<b>Note:</b> The complex value comes back expressly in this case. <br /><br /><br /><a name="4"></a><b>Example 1: Calling a Complex BLAS Level 1 Function from C</b><br />/* The following example illustrates a call from a C program to the complex BLAS Level 1 function zdotc(). This function computes the dot product of two double-precision complex vectors. <br /><br />In this example, the complex dot product is returned in the structure c. <br />*/ <br />#include "mkl.h" <br />#define N 5 <br />void main() <br />{ <br />int n, inca = 1, incb = 1, i; <br />typedef struct{ double re; double im; } complex16; <br />complex16 a[N], b[N], c; <br />void zdotc(); <br />n = N; <br />for( i = 0; i &lt; n; i++ ){ <br />a[i].re = (double)i; a[i].im = (double)i * 2.0; <br />b[i].re = (double)(n - i); b[i].im = (double)i * 2.0; <br />} <br />zdotc( &amp;c, &amp;n, a, &amp;inca, b, &amp;incb ); <br />printf( "The complex dot product is: ( %6.2f, %6.2f) ", c.re, c.im ); <br />} <br /><br /><br /><a name="5"></a><b>Example 2: Calling a Complex BLAS Level 1 Function from C++</b><br />#include "mkl.h" <br />typedef struct{ double re; double im; } complex16; <br />extern "C" void zdotc (complex16*, int *, complex16 *, int *, complex16 *, int *); <br /><br />#define N 5 <br /><br />void main() <br />{ <br />int n, inca = 1, incb = 1, i; <br /><br />complex16 a[N], b[N], c; <br /><br />n = N; <br />for( i = 0; i &lt; n; i++ ){ <br />a[i].re = (double)i; a[i].im = (double)i * 2.0; <br />b[i].re = (double)(n - i); b[i].im = (double)i * 2.0; <br />} <br />zdo tc(&amp;c, &amp;n, a, &amp;inca, b, &amp;incb ); <br />printf( "The complex dot product is: ( %6.2f, %6.2f) ", c.re, c.im ); <br />} <br /><br /><br /><a name="6"></a><b>Example 3: Using the CBLAS Interface Instead of Calling BLAS Directly from C Programs</b><br />#include "mkl.h" <br />typedef struct{ double re; double im; } complex16; <br /><br />extern "C" void cblas_zdotc_sub ( const int , const complex16 *, <br /> const int , const complex16 *, const int, const complex16*); <br /><br />#define N 5 <br /><br />void main() <br />{ <br /><br />int n, inca = 1, incb = 1, i; <br /><br />complex16 a[N], b[N], c; <br />n = N; <br />for( i = 0; i &lt; n; i++ ){ <br />a[i].re = (double)i; a[i].im = (double)i * 2.0; <br />b[i].re = (double)(n - i); b[i].im = (double)i * 2.0; <br />} <br />cblas_zdotc_sub(n, a, inca, b, incb,&amp;c ); <br />printf( "The complex dot product is: ( %6.2f, %6.2f) ", c.re, c.im ); <br />}</td>
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