Avoid excess code RISC-ification on the Pentium® 4 processor with the Microsoft Visual Studio* C++ .NET* 2003 compiler. RISC-ification is a compiler optimization that was developed for the Pentium® processor. Code would be RISC-ified, scheduled for U-V pipelines, and then CISC-ified to restore code in cases where no scheduling opportunities arose.
RISC-ification involves breaking complex instructions into a sequence of simpler ones. A RISC-ified sequence typically performs operations on data that are in registers, and the only references to memory are through explicit loads and stores. CISC-ification is simply the inverse of RISC-ification, and it has the advantage of reducing code bulk and instruction decoding/processing time. The following figure illustrates code RISC-ification using x86 instructions:
Disable RISC-ification in the compiler. The Pentium 4 processor is more efficient when executing CISC-ified code than it is executing RISC-ified sequences. The original purpose for RISC-ifying was to schedule for U-V pipelines. This requirement no longer exists. With RISC-ification enabled, we run the chance of disrupting code patterns following scheduling or other optimizations. This can make later CISC-ification difficult. Using the previous example, it is quite feasible for the scheduler to intermix the last (unrelated) MOV into the RISC-ified ADD sequence. As shown in the figure below, this may result in a missed CISC-ification pattern:
Optimizations for Pentium® 4 Processor in Microsoft* Visual Studio* C++ .NET* 2003 Compiler