Satisfy system-programming model and requirements for SSE3 instructions. The SSE3 Instructions state requires no new OS support for saving and restoring the new state during a context switch, beyond that provided for Streaming SIMD Extensions (SSE).
Enable the operating system or executive to provide support for initializing the processor to use Prescott New Instruction extensions, to handle the FXSAVE and FXRSTOR state-saving instructions, and to handle SIMD floating-point exceptions.
- Enabling SSE3 Instruction Support in a System Executive - Eleven of the thirteen new instructions are extensions to Streaming SIMD Extensions (SSE) and Streaming SIMD Extensions 2 (SSE2) technologies. Providing operating system or executive support for SSE3 Instruction technology is similar to the steps described in "General Guidelines for Adding Support to an Operating System for the SSE and SSE2 Extensions," Chapter 12 of The IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide. The steps are as follows:
- Check that the processor supports SSE, SSE2, and SSE3.
- Check that the processor supports FXSAVE and FXRESTOR.
- Provide a procedure that initializes the SSE and SSE2 state.
- Provide support for FXSAVE and FXRSTOR.
- Provide support (if necessary) in non-numeric exception handlers for exceptions generated by SSE, SSE2, and SSE3.
- Provide a handler for the SIMD floating-point exception (#XF).
- FXSAVE/FXRSTOR Replaces Use of FSAVE/FRSTOR - The FSAVE instruction does not save the new state associated with SSE/SSE2. FSAVE/FRSTOR should be replaced with FXSAVE/FXRSTOR; the new instructions save and restore 128-bit registers. For example, exception handlers that use 64-bit integer MMX™ technology or x87-FP operations are a case where FSAVE/FRSTOR should be replaced by FXSAVE/FXRSTOR.
- Initialization - The steps required for a system executive to initialize support for SSE3 instructions are the same as the initialization steps required to support SSE and SSE2 extensions. See Initialization of the SSE and SSE2 Extensions in Chapter 12 of The IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide.
- Exception Handler - Prescott New Instructions do not introduce new exception types.
- DEVICE NOT AVAILABLE (DNA) EXCEPTIONS - SSE3 Instructions will cause a DNA Exception (#NM) if the processor attempts to execute an SSE3 instruction while CR0.TS is set. If CPUID.PNI is clear, execution of any SSE3 instructions will cause an invalid opcode fault, regardless of the state of CR0.TS.
- NUMERIC ERROR FLAG AND IGNNEtf - Most of the SSE3 instructions ignore CR0.NE (they treat it as if it were always set) and the IGNNE# pin. They use the vector 19 software exception for error reporting. The exception is FISTTP. This instruction behaves like other x87-FP instructions.
- TECHNOLOGY EMULATION - The CR0.EM bit used to emulate floating-point instructions cannot be used in the same way for MMX technology emulation. If a Prescott New Instruction executes when the CR0.EM bit is set, an Invalid Opcode exception (Int 6) is generated instead of a Device Not Available exception (Int 7).
- Detecting Support for MONITOR/MWAIT - To use the MONITOR/MWAIT instruction, system software must detect support for these instructions using the CPUID instruction. The extended feature flag bit 3 [CPUID Function 01, ECX:3] indicates support for the MONITOR/MWAIT instructions. Software must also query CPUID's MONITOR/MWAIT leaf to obtain the monitor-line size information.
A separate item, How to Implement the Application Programming Model for Streaming SIMD Extensions 3 Instructions, is useful in conjunction with this one.