Intel® C++ STM Compiler, Prototype Edition 3.0

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Last Modified On :   May 16, 2009 3:57 PM PDT
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Product Overview

Parallel programming has traditionally been considered using locks to synchronize concurrent access to shared data. Lock-based synchronization, however, has known pitfalls: using locks for fine-grain synchronization and composing code that already uses locks are both difficult and prone to deadlock. Transactional memory is proposed to simplify parallel programming by supporting "atomic" and "isolated" execution of user-specified tasks. It provides an alternate concurrency control mechanism that avoids these pitfalls and eases parallel programming. The Transactional Memory C++ language constructs that are included open the door for users to exercise the new language constructs for parallel programming, understand the transaction memory programming model, and provide feedback on the usefulness of these extensions with Intel® C++ STM Compiler Prototype Edition. This posting includes the Intel® C++ STM Compiler Prototype Edition 2.0 and runtime libraries for Intel transactional memory language construct extensions.
Flash Demo
Sample Code

(1) A sample program in C++ with C++ virtual function using STM language extensions and OpenMP

Command Line:

Windows*: icl –Qtm_enabled –Qopenmp intel_stmtest_virtual.cpp –o virtual
./virtual.exe
Linux*: icc –Qtm_enabled –openmp intel_stmtest_virtual.cpp –o virtual
./virtual

intel_stmtest_virtual.cpp (2.16KB)

(2) A sample program in C using STM language extensions and OpenMP

Command Line:

Windows*: icl –Qtm_enabled -Qstd=c99 –Qopenmp intel_stmtest_hashtable.c –o hashtable
./hashtable.exe 229 1000000 10000
Linux*: icc –Qtm_enabled –openmp intel_stmtest_hashtable.cpp –o hashtable
./hashtable 229 1000000 10000

Usage: hashtable [<size of hashtable> [<number of items> [<number of duplicates>]]]
size of hashtable : number of buckets
number of items: total number of items we try to insert and remove from the hashtable
number of duplicates: number of those items that are duplicates.

intel_stmtest_hashtable.c (11.7KB)

(3) A sample program in C using STM language extensions and pthreads on Linux*

Command Line:

Linux*: icc –Qtm_enabled –Wall intel_stmtest_counting.c –o counting -lpthread
./counting

intel_stmtest_counting.c (2.73KB)

Intel® Transactional Memory Application Binary Interface (TM ABI) Specification 1.0

Technical contacts: Ali-Reza Adl-Tabatabai and Xinmin Tian

Intel® TM ABI specification 1.0 aims to define an application binary interface between IA32 and Intel(R)64 assembler level code, and the transactional memory library. The code may either have been written by an expert user in assembler, or may be the output of a native code compiler, binary translation or a JIT (though binary translation or a JIT may have more options for inlining than we contemplate here, and they are not expected to be the primary users of this specification). One of key motivations of publishing Intel® TM ABI specification is that we would like to enable the same user code to be linked against different implementations of the transactional memory system without requiring recompilation. Ideally we would like to be able to change the TM implementation used by a program at load time by choice of dynamic library, though that may prove to have too large a performance overhead to be feasible.

Intel TM ABI 1_0_1 (425k PDF)

Implementation Notes: Intel® Transactional Memory Application Binary Interface (TM ABI) Specification 1.0 has been implemented in Intel® C++ STM Compiler, Prototype Edition 3.0 for Windows* and Linux*

Technical Requirements

For the Windows* and Linux* version of this offering, you can find technical requirements here.

Frequently Asked Questions

Q - What is new with Edition 3.0?

A - Intel® C++ STM Compiler, Prototype Edition 3.0 for IA-32 (Windows* and Linux*) and Intel®64 (Windows* and Linux*)

1st-class language extensions for transactions

Based on the latest production Intel® C/C++ compiler 11.0

TM support for C++

  • Classes, inheritance, virtual functions, templates, exception handling, failure atomicity, TM memory allocation, Irrevocable actions for legacy code & I/O.

What is new in Prototype Edition 3.0?

  • New language constructs __tm_atomic { …} else { … } and __tm_wavier {…}
  • New function annotations __tm_safe, and tm_wrapping with support for registering commit and undo handlers for writing advanced transactional libraries
  • Transactional C++ new/delete, constructor and destructor support
  • TM annotation for template classes
  • Support for abort-on-exception semantics with explicit _tm_abort throw <exception>
  • New compiler and runtime optimizations
  • Support for transactional C++ STL library

Specification for the Intel® compiler-Runtime TM ABI 1.0.1

Download from whatif.intel.com

  • Use for experimentation & workload development
  • Provide feedback on language extensions

Q - What is new with Edition 2.0?

A - The Intel® C++ STM Compiler, Prototype Edition 2.0 for IA-32 and Intel®64

  • Enhanced integration of transactional memory features into C++ such as the TM support for C++ class annotation, inheritance, virtual functions, templates etc. and supporting failure atomicity, requiring less source code changes required to use TM constructs and annotations in C++ programs.
  • The ability to call legacy, non-transactional functions from inside a transaction, simplifying the use of transactions with existing code at the cost of serializing if such functions are called.
  • New, transaction-specific compiler optimizations and STM runtime library algorithms.
  • Transactional malloc/calloc/ralloc and free support for the use of malloc and free inside transactions providing the correct transactional semantics for these functions.
  • Runtime statistics gathering to aid performance tuning of transactional programs

Q - What does STM stand for?

A - STM stands for Software Transactional Memory, a promising technology to help accelerate the creation of parallel applications. STM will benefit from additional real world testing and feedback to assist developers new to parallel programming.

Q - What are some of the prerequisites to using these extensions?

A - These extensions are for C and C++ programmers on Windows* and Linux*, using Intel’s production compiler.

Q - Do I have to buy the Intel® Compiler to use these?

A - No, you don't. You just need to make sure that you have an active license of the Intel® C++ Compiler for Windows* or the Intel® C++ Compiler for Linux* on your system. If you don't, you can easily acquire a commercial license or try an evaluation copy.

Q - What should I expect?

A - This is an ideal tool for general experimentation, testing and industry dialogue around real results. It’s a great opportunity to explore Software Programming Models for parallel programming.

Q - How do I get support?

A - You are welcome to join our What If forum and post your question. The team will keep any eye on the discussion and do our best to answer your questions.

Q - What are the licensing terms that spell out how exactly I can use this utility?

A - The licensing terms are listed on the download page.

Primary Technology Contacts

Robert Geva
Principal Engineer at Intel’s Software and Solutions Group. Robert joined Intel in 1991 and has since developed an expertise in compilers and performance analysis and tuning for microarchitectures. Robert has worked on compiler optimizations for a variety of Intel® microprocessor based systems, including the 80486, the Pentium® processor, the Pentium® Pro Processor, Itanium® processor, the Pentium® 4 and Pentium® M processors. Robert is a software architect within the Intel Developer Products Division that is developing the transactional memory technology. Robert has BA and MSc degrees from the Technion, Israel Institute of Technology.

Ali-Reza Adl-Tabatabai
Senior Principal Engineer in Intel’s Programming Systems Lab, Ali leads a team of researchers working on compilers and scalable runtimes for future Intel® architectures. Ali has spent most of his career building high-performance programming language implementations, including static and dynamic optimizing compilers and language runtime systems. His current research concentrates on language features that make it easier for the mainstream developer to build reliable and scalable parallel programs for future multi-core architectures and on architectural support for those features. Most recently he has worked on transactional memory, a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. Ali has published over 20 papers in leading conferences and journals. He received his PhD in Computer Science from Carnegie Mellon University.

Xinmin Tian
Principal Engineer and Compiler Architect at Intel, currently Xinmin Tian leads parallelizati on, OpenMP*, vectorization and transactional memory development projects for Intel® C++/FORTRAN compilers for Intel® IA-32, Intel® 64, and Itanium® multi-core processors. He has over 30 refereed technical publications on compiler optimizations, parallel computing, and multithreaded architectures. He is a coauthor of "The Software Optimization Cookbook" (Second Edition) at Intel Press, published in 2006, and a main contributor for the "Multi-Core Programming" book published by Intel Press in 2006. He holds a PhD in Computer Science and has 20 patents pending in the areas of compiler optimizations, parallelization, and multi-core architectures. He also served on program committees for research conferences and has served as a referee for technical journals and conferences.