zlib	ipp_zlib
1	fast
2	linked to fast
3	linked to fast
4	average
5	linked to average
6	default
7	linked to default
8	linked to best
9	best

While in previous release, IPP_zlib use the level 5 as default. Some users may notice that the previous version have higher speed, but less compression level. So in order to align with zlib (www.zlib.net), Intel® IPP 7.0 provide compression ratio for each IPP_zlib compression level not less than it is in zlib.

Additionally, Intel® IPP 7.0 also improved the encoding performance of ipp_zlib with new default compression level. And new high-level data compression libraries (bzip2, gzip and lzo) are supported Intel® IPP 7.0.

Hand-tuned optimizations designed to maximize performance of the Intel IPP library on Intel Atom processors were added beginning with v6.0 of the Intel IPP library. For maximum performance on Intel Atom processors, we recommend that you upgrade to version 7.0 of the Intel IPP library.

Both static and dynamic/shared libraries in v7.0 of the Intel IPP library include Intel Atom processor optimizations. Applications linked with versions 7.0 of the Intel IPP library will be dispatched to the "s8" optimized library for IA-32 and the "n8" library for Intel® 64 whenever your application executes on an Intel Atom processor.

For more information regarding dispatching please see Understanding CPU Dispatching in the Intel® IPP Library or check the Intel IPP Getting_Started.htm and userguide_*.pdf files in the Intel IPP documentation.

In the v6.x Intel IPP library, only the dynamic/shared libraries contain Intel Atom processor optimizations; there are no Intel Atom processor optimizations in the v6.x dispatched static libraries. However, the v6.x dispatched static libraries will safely run on an Intel Atom processor by dispatching to the v8/u8 libraries optimized for the Merom microarchitecture (Intel Core 2 processor), which is also designed for use with the same Intel Supplemental SSE3 SIMD instruction set (SSSE3) that Intel Atom processors support. A separate non-dispatched static Intel IPP library for Linux* is available on the IA-32 platform (and as part of the Intel Atom SDK).

The following list of functions have been hand-optimized for the Intel Atom processor for the version of the Intel IPP library listed at the beginning of this article.

Note: every Intel IPP library primitive is available for use with the Intel Atom processor, this list simply shows those functions which have been specially hand-tuned for the Intel Atom processor; hand-tuning is not required to achieve optimum performance for all IPP functions. If you have some specific Intel IPP functions that are not listed in the following table, and would like to see them added to the priority list for Atom optimization, please create a thread on the IPP forum stating which functions you would like to see added to the Atom optimization priority list.

ippsAddProduct_32f
ippsAddProduct_32fc
ippsAddProduct_32s_Sfs
ippsAddProduct_64f
ippsAddProduct_64fc
ippsAdd_32f    
ippsAdd_32fc   
ippsAdd_64f    
ippsAdd_64fc
ippsAdd_32f_I
ippsAdd_32fc_I
ippsAdd_32s_Sfs
ippsConvert_16s32f
ippsConvert_16u32f
ippsConvert_32f16s_Sfs
ippsConvert_32f16u_Sfs
ippsConvert_32f32s_Sfs
ippsConvert_32f8s_Sfs
ippsConvert_32f8u_Sfs
ippsConvert_32s32f
ippsConvert_32s64f
ippsConvert_64f32s_Sfs
ippsConvert_8s32f
ippsConvert_8u32f
ippsCopy_16s
ippsCopy_64s
ippsDFTFwd_CToC_32fc
ippsDFTFwd_CToC_64fc
ippsDiv_16sc_Sfs
ippsDiv_16s_Sfs
ippsDiv_16u_Sfs
ippsDiv_32f
ippsDiv_32fc
ippsDiv_32s16s_Sfs
ippsDiv_32s_Sfs
ippsDiv_64f
ippsDiv_64fc
ippsDotProd_32f32fc64fc
ippsDotProd_32f64f
ippsDotProd_32fc64fc
ippsDotProd_64f
ippsDotProd_64f64fc
ippsDotProd_64fc
ippsFFTFwd_CToC_32fc
ippsFFTFwd_CToC_64fc
ippsFilterMedian_32f
ippsFilterMedian_32s
ippsFilterMedian_64f
ippsFIR32f_16s_Sfs
ippsFIR64f_16s_Sfs
ippsFIR64f_32s_Sfs
ippsFIR_32f
ippsFIR_64f
ippsJoin_32f16s_D2L
ippsLShiftC_32s_I
ippsMax_32s
ippsMean_32f
ippsMin_32s
ippsMul_32f       
ippsMul_32fc      
ippsMul_64f       
ippsMul_64fc
ippsMul_32f_I
ippsMulC_32f
ippsMulC_32f_I
ippsNorm_L2_32f
ippsNormDiff_L2_32f
ippsRShiftC_32s_I
ippsSampleUp_32f
ippsScale_32f_I
ippsSqr_32f
ippsSqr_32f_I
ippsSqr_32fc
ippsSqr_64f
ippsSqr_64fc
ippsSqrt_16s_Sfs
ippsSqrt_16u_Sfs
ippsSqrt_32f
ippsSqrt_32f_I
ippsSqrt_32fc
ippsSqrt_64f
ippsSqrt_64fc
ippsSub_32s_Sfs
ippsSub_32f       
ippsSub_32f_I
ippsSub_32fc      
ippsSub_64f       
ippsSub_64fc      
ippsSum_32f
ippsSum_32f
ippsThreshold_LTVal_32f_I

ippsAdaptiveCodebookSearch_RTA_32f
ippsSBADPCMEncode_G722_16s
ippsSBADPCMDecode_G722_16s
ippsDCTFwd_G7221_16s
ippsDCTInv_G7221_16s
ippsDecomposeDCTToMLT_G7221_16s
ippsDecomposeMLTToDCT_G7221_16s
ippsEnvelopFrequency_G7291_16s
ippsFilterHighpass_G7291_16s
ippsFilterLowpass_G7291_16s
ippsFIRSubbandLow_EC_32sc_Sfs
ippsFIRSubbandLowCoeffUpdate_EC_32sc_I
ippsFixedCodebookSearch_RTA_32f
ippsFixedCodebookSearchRandom_RTA_32f
ippsLSPToLPC_RTA_32f
ippsLSPQuant_RTA_32f
ippsMDCTFwd_G7291_16s
ippsMDCTPostProcess_G7291_16s
ippsQMFDecode_G722_16s
ippsQMFDecode_G7291_16s
ippsQMFEncode_G722_16s
ippsQMFEncode_G7291_16s
ippsSubbandAnalysis_16s32sc_Sfs
ippsSubbandController_EC_32f
ippsSubbandControllerUpdate_EC_32f
ippsSubbandSynthesis_32sc16s_Sfs
ippsTiltCompensation_G7291_16s
ippsToeplizMatrix_G729_32f
ippsToneDetect_EC_32f

ippsCRC32_8u
ippsEncodeRLE_BZ2_8u
ippsReduceDictionary_8u_I
ippsVLCCountBits_16s32s
ippsVLCDecodeOne_1u16s
ippsVLCDecodeUTupleBlock_1u16s
ippsVLCDecodeUTupleOne_1u16s
ippsVLCEncodeInit_32s

ippsMDCTInvWindow_MP3_32s
ippsPow43Scale_16s32s_Sf
ippsPow43_16s32f
ippsPredictCoef_SBR_C_32fc_D2L
ippsSynthesisDownFilter_SBR_CToR_32fc32f_D2L
ippsSynthesisDownFilter_SBR_RToR_32f_D2L
ippsSynthesisFilter_PQMF_MP3_32f
ippsSynthesisFilter_SBR_CToR_32fc32f_D2L
ippsSynthesisFilter_SBR_RToR_32f_D2L
ippsVLCDecodeEscBlock_AAC_1u16s
ippsVLCDecodeEscBlock_MP3_1u16s
ippsVLCDecodeUTupleEscBlock_AAC_1u16s
ippsVLCDecodeUTupleEscBlock_MP3_1u16s

ippiAdd_16s_C1IRSfs
ippiConvert_16u32f_C1R 
ippiConvert_16u8u_C3R 
ippiConvert_8u16s_C1R
ippiConvert_8u16u_C1R 
ippiCopyReplicateBorder_16s_C1R
ippiCopy_8u_C1R 
ippiCopy_8u_C3R 
ippiCopy_8u_C4R 
ippiDilate_32f_AC4R 
ippiDilate_32f_C1R 
ippiDilate_32f_C3R 
ippiDiv_16s_AC4RSfs 
ippiDiv_16s_C1RSfs 
ippiDiv_16s_C3RSfs 
ippiDiv_16s_C4RSfs 
ippiDiv_16u_AC4RSfs 
ippiDiv_16u_C1RSfs 
ippiDiv_16u_C3RSfs 
ippiDiv_16u_C4RSfs 
ippiDiv_32f_AC4R 
ippiDiv_32f_C1R 
ippiDiv_32f_C3R 
ippiDiv_32f_C4R 
ippiErode_32f_AC4R 
ippiErode_32f_C1R 
ippiErode_32f_C3R 
ippiFilter32f_8u_AC4R
ippiFilter32f_8u_C1R 
ippiFilter32f_8u_C3R 
ippiFilter32f_8u_C4R 
ippiFilterGauss_16s_AC4R 
ippiFilterGauss_16s_C1R 
ippiFilterGauss_16s_C3R 
ippiFilterGauss_16s_C4R 
ippiFilterGauss_32f_AC4R 
ippiFilterGauss_32f_C1R 
ippiFilterGauss_32f_C3R 
ippiFilterGauss_32f_C4R 
ippiFilter_16s_AC4R 
ippiFilter_16s_C1R 
ippiFilter_16s_C3R 
ippiFilter_16s_C4R 
ippiFilter_16u_AC4R 
ippiFilter_16u_C1R 
ippiFilter_16u_C3R 
ippiFilter_16u_C4R 
ippiFilter_8u_AC4R 
ippiFilter_8u_C1R 
ippiFilter_8u_C3R 
ippiFilter_8u_C4R 
ippiGetPerspectiveQuad
ippiMirror_16u_C1IR
ippiMirror_16u_C4R 
ippiMirror_32s_C4R 
ippiMirror_8u_C4R 
ippiMul_32f_AC4R 
ippiMul_32f_C1R 
ippiMul_32f_C3R 
ippiMul_32f_C4R 
ippiSet_16u_C3R 
ippiSet_16u_C4R 
ippiSet_32f_C1R 
ippiSet_32f_C3R 
ippiSet_8u_C3R 
ippiSet_8u_C4R 
ippiSqrt_16s_AC4RSfs 
ippiSqrt_16s_C1RSfs 
ippiSqrt_16s_C3RSfs 
ippiSqrt_16u_AC4RSfs 
ippiSqrt_16u_C1RSfs 
ippiSqrt_16u_C3RSfs 
ippiSqrt_32f_AC4R 
ippiSqrt_32f_C1R 
ippiSqrt_32f_C3R 
ippiSqr_32f_AC4R 
ippiSqr_32f_C1R 
ippiSqr_32f_C3R 
ippiSqr_32f_C4R 
ippiSub_16s_C1IRSfs

ippiBGR555ToYCbCr420_16u8u_C3P3R
ippiBGR555ToYCbCr422_16u8u_C3C2R
ippiBGR555ToYCbCr422_16u8u_C3P3R
ippiBGR555ToYCrCb420_16u8u_C3P3R
ippiBGR555ToYUV420_16u8u_C3P3R
ippiBGR565ToYCbCr411_16u8u_C3P3R
ippiBGR565ToYCbCr420_16u8u_C3P3R
ippiBGR565ToYCbCr422_16u8u_C3C2R
ippiBGR565ToYCbCr422_16u8u_C3P3R
ippiBGR565ToYCrCb420_16u8u_C3P3R
ippiBGR565ToYUV420_16u8u_C3P3R
ippiBGRToCbYCr422_8u_AC4C2R
ippiBGRToHLS_8u_AC4P4R
ippiBGRToHLS_8u_AP4C4R
ippiBGRToHLS_8u_AP4R
ippiBGRToHLS_8u_C3P3R
ippiBGRToHLS_8u_P3C3R
ippiBGRToHLS_8u_P3R
ippiBGRToYCbCr422_8u_AC4C2R
ippiBGRToYCbCr422_8u_AC4P3R
ippiBGRToYCbCr422_8u_C3C2R
ippiBGRToYCbCr422_8u_C3P3R
ippiCbYCr422ToBGR_8u_C2C4R
ippiHLSToBGR_8u_AC4P4R
ippiHLSToBGR_8u_AP4C4R
ippiHLSToBGR_8u_AP4R
ippiHLSToBGR_8u_C3P3R
ippiHLSToBGR_8u_P3C3R
ippiHLSToBGR_8u_P3R
ippiRGB565ToYUV422_16u8u_C3P3R
ippiRGBToCbYCr422Gamma_8u_C3C2R
ippiRGBToCbYCr422_8u_C3C2R
ippiRGBToYCbCr422_8u_C3C2R
ippiRGBToYCbCr422_8u_C3P3R
ippiRGBToYCbCr_8u_P3R
ippiRGBToYCrCb422_8u_P3C2R
ippiRGBToYUV420_8u_P3
ippiRGBToYUV420_8u_P3R
ippiRGBToYUV422_8u_C3C2R
ippiRGBToYUV422_8u_C3P3
ippiRGBToYUV422_8u_C3P3R
ippiRGBToYUV422_8u_P3
ippiRGBToYUV422_8u_P3R
ippiRGBToYUV_8u_AC4R
ippiRGBToYUV_8u_C3R
ippiRGBToYUV_8u_P3R
ippiYCbCr422To420_Interlace_8u_P3R
ippiYCbCr422ToBGR_8u_C2C3R
ippiYCbCr422ToBGR_8u_C2P3R
ippiYCbCrToRGB_8u_P3R
ippiYUV422ToRGB_8u_P3C3
ippiYUV422ToRGB_8u_P3C3R
ippiYUVToRGB_8u_P3C3R

ippiReconstructLumaIntra4x4_H264High_32s16u_IP1R
ippiFilterDeblockingLumaVerEdge_H264_16u_C1IR
ippiFilterDeblockingLumaHorEdge_H264_16u_C1IR

ippsFindCAny_8u
ippmInvert_m_32f
ippmMul_tm_32f

Functions not listed above are either hand-optimized for the Merom microarchitecture (SSSE3) or for prior SIMD instruction sets that are compatible with the Intel Atom processor (such as SSE2). In addition, the entire Intel Atom optimized library is compiler-optimized for the Intel Atom processor using the Intel Compiler xSSE3_ATOM switch (enable Atom optimizations) in order to take advantage of features unique to the Intel Atom processor.

Please see Optimized for the Intel® Atom™ Processor with Intel's Compiler for more information and check out the Intel Parallel Studio web site where you can learn more about the tools available to develop, debug, and tune your multi-threaded applications.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

The table below reflects the Intel AVX support provided in the Intel IPP 7.0.2 library release.

Intel AVX optimized code is available in both the 32-bit and 64-bit editions of the 7.0 library.

There is very limited support for Intel AVX in the 6.1 library; if you plan to use Intel IPP on an Intel AVX platform you should upgrade to the 7.0 version of the Intel IPP library.

Intel® AVX (Intel® Advanced Vector Extensions) is a 256-bit instruction set extension to SSE designed to provide even higher performance for applications that are floating-point intensive. Intel AVX adds new functionality to the the existing Intel SIMD instruction set (based on SSE) and includes a more compact SIMD encoding format. A large number (200+) of Intel SSEx instructions have been "upgraded" in AVX to take advantage of features like a distinct destination operand and flexible memory alignment. Approximately 100 of the legacy 128-bit Intel SSEx instructions have been promoted to process 256-bit vector data. In addition, approximately 100 new data processing and arithmetic operations, not present in the legacy Intel SSEx SIMD instruction set, have been added.

The primary benefits of Intel AVX are:

• Support for wider vector data (up to 256-bit).
• Efficient instruction encoding scheme that supports 3 and 4 operand instruction syntaxes.
• Flexible programming environment, ranging from branch handling to relaxed memory alignment requirements.
• New data manipulation and arithmetic compute primitives, including broadcast, permute, fused-multiply-add, etc.
  
  

ippGetCpuFeatures() reports information regarding the SIMD features available to your processor. Alternatively, ippGetCpuType() detects the processor type in your system. A return value of ippCpuAVX means your processor supports the Intel AVX instruction set. These functions are declared in ippcore.h.

Mask the value returned by ippGetCpuFeatures() with ippCPUID_AVX (0x0100) to determine if the Intel AVX SIMD instructions are supported by your processor (ippGetCpuFeatures() & ippCPUID_AVX is TRUE). To determine if your operating system also supports the Intel AVX instructions (saves the extended SIMD registers), mask the returned value from ippGetCpuFeatures() with ippAVX_ENABLEDBYOS (0x0200). Both conditions (i.e., CPU and OS support) must be met before your application can utilize the Intel AVX SIMD instructions.

The Intel IPP library has been optimized for a variety of SIMD instruction sets. Automatic "dispatching" detects the SIMD instruction set that is available on the running processor and selects the optimal SIMD instructions for that processor. Please review Understanding CPU Dispatching in the Intel® IPP Library for more information regarding dispatching.

Intel AVX optimization in the Intel IPP library consists of "hand-optimized" and "compiler-tuned" functions – code that has been directly optimized for the Intel AVX instruction set. Given the large number of primitives in the Intel IPP library, it is impossible to directly optimize every Intel IPP function for the large set of new instructions represented by the Intel AVX instruction set within the period of a single product release or update (processor-specific optimizations may also take into consideration cache size and number of cores/threads). Therefore, the functions in the table below represent those that either receive the greatest benefit from the new Intel AVX instructions or are the most widely used by Intel IPP customers.

If you have some specific Intel IPP functions that are not listed in the following table, and would like to see them added to the priority list for future AVX optimization, please create a thread on the IPP forum stating which functions you would like to see added to the AVX optimization priority list.

Functions directly optimized for Intel AVX are added to the table below as they become available with each new release or update of the library.

The following conventions are used in the table below to allow multiple similar functions to be denoted on a single line:

• {x} - Braces enclose a required (function name) element.
• [x] - Square brackets enclose an optional (function name) element.
• | - A vertical line indicates an exclusive choice within a set of optional or required elements.
• {x|y|z} - Example of three mutually exclusive choices within a required element in the function name.
• [x|y|z] - Example of three mutually exclusive choices within an optional element in the function name.

ippsAbs_{16s|32s|32f|64f}[_I] 
ippsAdd_{32f|32fc|64f|64fc}[_I] 
ippsAddC_{32f|64f}[_I] 
ippsAddProductC_32f 
ippsAddProduct_{32fc|64f|64fc} 
ippsAutoCorr_{32f|64f}
ippsConv_32f 
ippsConvert_{8s|8u|16s|16u|32s|64f}32f 
ippsConvert_{32s|32f}64f 
ippsConvert_32f{8s|8u|16s|16u}_Sfs 
ippsConvert_64f32s_Sfs 
ippsCopy_{16s|32s|32f|64f} 
ippsCrossCorr_{32f|64f} 
ippsDFTFwd_CToC_{32f|32fc|64f|64fc} 
ippsDFTFwd_RTo{CCS|Pack|Perm}_{32f|64f} 
ippsDFTInv_CCSToR_{32f|64f} 
ippsDFTInv_CToC_{32f|32fc|64f|64fc} 
ippsDFTInv_{Pack|Perm}ToR_{32f|64f} 
ippsDFTOutOrd{Fwd|Inv}_CToC_{32fc|64fc} 
ippsDiv[C]_32f[_I] 
ippsDotProd_32f64f 
ippsFFTFwd_CToC_{32f|32fc|64f|64fc}[_I] 
ippsFFTFwd_RTo{CCS|Pack|Perm}_{32f|64f}[_I] 
ippsFFTInv_CCSToR_{32f|64f}[_I] 
ippsFFTInv_CToC_{32f|32fc|64f|64fc}[_I] 
ippsFFTInv_{Pack|Perm}ToR_{32f|64f}[_I] 
ippsFIR64f_32f[_I] 
ippsFIR64fc_32fc[_I] 
ippsFIRLMS_32f 
ippsFIR_{32f|32fc|64f|64fc}[_I] 
ippsIIR32fc_16sc_[I]Sfs 
ippsIIR64fc_32fc[_I] 
ippsIIR_32f[_I] 
ippsLShiftC_16s_I 
ippsMagnitude_16sc_Sfs 
ipps{Min|Max}Indx_{32f|64f} 
ippsMul_32fc[_I] 
ippsMul[C]_{32f|32fc|64f|64fc}[_I] 
ippsMulC_64f64s_ISfs 
ipps{Not|Or}_8u 
ippsPhase_{16s|16sc|32sc}_Sfs 
ippsPowerSpectr_{32f|32fc} 
ippsRShiftC_16u_I 
ippsSet_{8u|16s|32s} 
ippsSqr_{8u|16s|16u|16sc}_[I]Sfs 
ippsSqr_{32f|32fc|64f|64fc}[_I] 
ippsSqrt_32f[_I] 
ippsSub_{32f|32fc|64f|64fc}[_I] 
ippsSubC_{32f|32fc|64f|64fc}[_I] 
ippsSubCRev_{32f|32fc|64f|64fc}[_I] 
ippsSum_{32f|64f} 
ippsThreshold_{32f|GT_32f|LT_32f}_[_I] 
ippsThreshold_{GT|LT}Abs_{32f|64f}[_I] 
ippsThreshold_GTVal_32f[_I] 
ippsWinBartlett_{32f|32fc|64f|64fc}[_I] 
ippsWinBlackman_{32f|64f|64fc}[_I] 
ippsWinBlackmanOpt_{32f|64f|64fc}[_I] 
ippsWinBlackmanStd_{32f|64f|64fc}[_I] 
ippsWinKaiser_{32f|64f|64fc}[_I] 
ippsZero_{8u|16s|32f}

ippgDFTFwd_CToC_8_64fc ippgDFTFwd_CToC_12_64fc 
ippgDFTFwd_CToC_16_{32fc|64fc}
ippgDFTFwd_CToC_20_64fc
ippgDFTFwd_CToC_24_64fc
ippgDFTFwd_CToC_28_64fc 
ippgDFTFwd_CToC_32_{32fc|64fc}
ippgDFTFwd_CToC_36_64fc
ippgDFTFwd_CToC_40_64fc
ippgDFTFwd_CToC_44_64fc 
ippgDFTFwd_CToC_48_{32fc|64fc}
ippgDFTFwd_CToC_52_64fc 
ippgDFTFwd_CToC_56_64fc 
ippgDFTFwd_CToC_60_64fc 
ippgDFTFwd_CToC_64_{32fc|64fc} 
ippgDFTInv_CToC_8_64fc 
ippgDFTInv_CToC_12_64fc 
ippgDFTInv_CToC_16_{32fc|64fc} 
ippgDFTInv_CToC_20_64fc 
ippgDFTInv_CToC_24_64fc 
ippgDFTInv_CToC_28_64fc 
ippgDFTInv_CToC_32_{32fc|64fc} 
ippgDFTInv_CToC_36_64fc 
ippgDFTInv_CToC_40_64fc 
ippgDFTInv_CToC_44_64fc 
ippgDFTInv_CToC_48_{32fc|64fc} 
ippgDFTInv_CToC_52_64fc 
ippgDFTInv_CToC_56_64fc 
ippgDFTInv_CToC_60_64fc 
ippgDFTInv_CToC_64_{32fc|64fc}

iippsDeinterleave_32f

ippsAdaptiveCodebookSearch_RTA_32f
ippsFixedCodebookSearch_RTA_32f
ippsFixedCodebookSearchRandom_RTA_32f
ippsHighPassFilter_RTA_32f
ippsLSPQuant_RTA_32f
ippsLSPToLPC_RTA_32f
ippsPostFilter_RTA_32f_I
ippsQMFDecode_RTA_32f
ippsSynthesisFilter_G729_32f

ippiRGBToHLS_8u_AC4R
ippiRGBToHLS_8u_C3R

ipprCastEye_32f
ipprCastShadowSO_32f
ipprDot_32f_P3C1M
ipprHitPoint3DEpsM0_32f_M
ipprHitPoint3DEpsS0_32f_M
ipprMul_32f_C1P3IM

ippiEigenValsVecs_[8u]32f_C1R 
ippiFilterGaussBorder_32f_C1R 
ippiMinEigenVal_[8u]32f_C1R 
ippiNorm_Inf_{8u|8s|16u|32f}_C{1|3C}MR 
ippiNorm_L1_{8u|8s|16u|32f}_C{1|3C}MR 
ippiNorm_L2_{8u|8s|16u|32f}_C{1|3C}MR 
ippiNormRel_L2_32f_C3CMR 
ippiUpdateMotionHistory_[8u|16u]32f_C1IR

ippiAddC_32f_C1[I]R 
ippiConvert_32f* 
ippiCopy_16s* 
ippiCopy_8u* 
ippiConvFull_32f_{AC4|C1|C3}R 
ippiConvValid_32f_{AC4|C1|C3}R 
ippiCrossCorrFull_NormLevel_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_64f_C1R 
ippiCrossCorrFull_NormLevel_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrFull_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrSame_NormLevel_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrSame_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrValid_{8u32f|8s32f|16u32f|32f}_C1R 
ippiCrossCorrValid_NormLevel_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_64f_C1R 
ippiCrossCorrValid_NormLevel_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrValid_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiDCT8x8FwdLS_8u16s_C1R 
ippiDCT8x8Fwd_16s_C1[I|R] 
ippiDCT8x8Fwd_32f_C1[I] 
ippiDCT8x8Fwd_8u16s_C1R 
ippiDCT8x8InvLSClip_16s8u_C1R 
ippiDCT8x8Inv_16s8u_C1R 
ippiDCT8x8Inv_16s_C1[I|R] 
ippiDCT8x8Inv_2x2_16s_C1[I] 
ippiDCT8x8Inv_32f_C1[I] 
ippiDCT8x8Inv_4x4_16s_C1[I] 
ippiDCT8x8Inv_A10_16s_C1[I] 
ippiDCT8x8To2x2Inv_16s_C1[I] 
ippiDCT8x8To4x4Inv_16s_C1[I] 
ippiDFTFwd_CToC_32fc_C1[I]R 
ippiDFTFwd_RToPack_32f_{AC4|C1|C3|C4}[I]R 
ippiDFTFwd_RToPack_8u32s_{AC4|C1|C3|C4}RSfs 
ippiDFTInv_CToC_32fc_C1[I]R 
ippiDFTInv_PackToR_32f_{AC4|C1|C3|C4}[I]R 
ippiDFTInv_PackToR_32s8u_{AC4|C1|C3|C4}RSfs 
ippiDilate3x3_32f_C1[I]R 
ippiDilate3x3_64f_C1R 
ippiDivC_32f_C1[I]R 
ippiDiv_32f_{C1|C3}[I]R 
ippiDotProd_32f64f_{C1|C3}R 
ippiErode3x3_64f_C1R 
ippiFFTFwd_CToC_32fc_C1[I]R 
ippiFFTFwd_RToPack_32f_{AC4|C1|C3|C4}[I]R 
ippiFFTFwd_RToPack_8u32s_{AC4|C1|C3|C4}RSfs 
ippiFFTInv_CToC_32fc_C1[I]R 
ippiFFTInv_PackToR_32f_{AC4|C1|C3|C4}[I]R 
ippiFFTInv_PackToR_32s8u_{AC4|C1|C3|C4}RSfs 
ippiFilter_32f_{C1|C3|C4}R 
ippiFilter_32f_AC4R 
ippiFilter_64f_{C1|C3}R 
ippiFilter32f_{8s|8u|16s|16u|32s}_C{1|3|4}R 
ippiFilter32f_{8u|16s|16u}_AC4R 
ippiFilter32f_{8s|8u}16s_C{1|3|4}R 
ippiFilterBox_8u_{C1|C3}R 
ippiFilterBox_32f_{C1|C4|AC4}R 
ippiFilterColumn32f_{8u|16s|16u}_{C1|C3|C4|AC4}R 
ippiFilterColumn_32f_{C1|C3|C4|AC4}R 
ippiFilterGauss_32f_{C1|C3}R 
ippiFilterHipass_32f_{C1|C3|C4|AC4}R 
ippiFilterLaplace_32f_{C1|C3|C4|AC4}R 
ippiFilterLowpass_32f_{C1|C3|AC4}R 
ippiFilterMax_32f_{C1|C3|C4|AC4}R 
ippiFilterMedian_32f_C1R 
ippiFilterMin_32f_{C1|C3|C4|AC4}R 
ippiFilterRow_32f_{C1|C3|C4|AC4}R 
ippiFilterRow32f_{8u|16s|16u}_{C1|C3|C4|AC4}R 
ippiFilterSobelHoriz_32f_{C1|C3}R 
ippiFilterSobelVert_32f_{C1|C3}R 
ippiMean_32f_{C1|C3}R 
ippiMulC_32f_C1[I]R 
ippiMul_32f_{C1|C3|C4}[I]R 
ippiResizeSqrPixel_{32f|64f}_{C1|C3|C4|AC4}R 
ippiResizeSqrPixel_{32f|64f}_{P3|P4}R 
ippiSqrDistanceFull_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiSqrDistanceSame_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiSqrDistanceValid_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiSqrt_32f_C1R 
ippiSqrt_32f_C3IR 
ippiSubC_32f_C1[I]R 
ippiSub_32f_{C1|C3|C4}[I]R 
ippiSum_32f_C{1|3}R 
ippiTranspose_32f_C1R

ippiPCTFwd_JPEGXR_32f_C1IR 
ippiPCTFwd16x16_JPEGXR_32f_C1IR 
ippiPCTFwd8x16_JPEGXR_32f_C1IR 
ippiPCTFwd8x8_JPEGXR_32f_C1IR 
ippiPCTInv_JPEGXR_32f_C1IR_128 
ippiPCTInv16x16_JPEGXR_32f_C1IR 
ippiPCTInv8x16_JPEGXR_32f_C1IR 
ippiPCTInv8x8_JPEGXR_32f_C1IR

Those functions that have not been directly optimized for AVX (i.e., functions that do not appear in the table) have been compiled using the Intel Compiler "xG" switch (enable AVX optimization). Additional performance improvements are achieved by adherence to an AVX ABI (application binary interface) feature that inserts the special AVX "vzeroupper" instruction after any function with AVX code to eliminate any AVX to SSE transition penalties.

For those functions that are not directly optimized for AVX, the g9/e9 library utilizes optimizations from prior compatible SSE optimizations, such as those tuned for the p8/y8 libraries and preceding SIMD optimizations (e.g., SSE4.x, AES-NI and SSE2/3). Thus, functions not listed above will include the highest level of directly optimized code based on the AES-NI, SSE4.x, SSSE3, SSE3 and SSE2 SIMD instruction sets, wherever applicable.

For more information about the g9/e9 optimization layer and Intel AVX in the Intel IPP library, please refer to the Intel Integrated Performance Primitives for Windows* OS on Intel® 64 Architecture 'User's Guide'.

Review How to Compile for Intel® AVX for more information and check out the Intel Parallel Studio web site where you can learn more about the tools available to develop, debug, and tune your multi-threaded applications.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

IMPORTANT! The minimum SIMD instruction levels supported by version 7.0 of the Intel IPP library has changed! Applications built with this version of the library require that processors must support at least the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instruction set when built for Intel IA-32 processors (ia32) and the Intel® Streaming SIMD Extensions 3 (Intel® SSE3) instruction set when built for Intel® 64 processors (intel64). The non-optimized layers of the library (px on ia32 and mx on intel64) have been removed; the w7 and m7 optimization layers are now the default optimization layers.

The standard distribution of the Intel IPP library contains multiple, functionally-identical, SIMD-specific, optimized libraries (or layers) that are automatically “dispatched” at run-time. The “dispatcher” directs your calls to the appropriate optimized library layer based on SIMD capabilities discovered during library initialization. This is done to maximize each function’s use of the runtime processor's underlying SIMD instructions and other architecture-specific features.

Note: you can build custom processor-specific libraries that do not require the dispatcher, but that is outside the scope of this article. Please read this IPP linkage models article for information on how to build custom versions of the IPP library.

Dispatching selects the Intel IPP optimized library layer that corresponds to the runtime CPU's SIMD instruction set. For example, on a Windows installation, the $(IPPROOT)\..\redist\intel64\ipp directory contains a file named ippiu8-7.0.dll which contains version ‘7.0’ of the optimized image processing libraries for processors that support the Intel SSE3 instructions on 64-bit processors; ‘ippi’ denotes the image processing domain, ‘u8’ denotes the SSSE3 instructions set for 64-bit processors and ‘7.0’ denotes the library’s version number.

In the general case, the “dispatcher” identifies the run-time processor only once, at library initialization time, and sets up a variable internal to the library that directs your calls to the SIMD-specific functions that match the runtime processor. For example, ippsCopy_8u(), has multiple implementations stored in the library, with each version optimized to a specific SIMD instruction set. The u8_ippsCopy_8u() version of ippsCopy_8u() is called by the dispatcher when running on an Intel® Core 2 Duo® processor in 64-bit addressing mode, because u8_ippsCopy_8u() is optimized for the SSSE3 instruction set architecture supported by that processor in 64-bit addressing mode.

Note: IPP architectures generally correspond to SIMD (MMX, SSE, AES, etc.) instructions sets, with some minor variations (see the p8 and y8 optimization layers).

Initializing the IPP Dispatcher

Identifying the runtime processor and initializing the dispatcher should be the first action you take with the Intel IPP library. If you are using the standard dynamic link library this process is handled automatically when the Intel IPP shared library is initialized. If you are using a static library you must perform this step manually. See this article on the ipp*Init*() functions for more information on how to do this.

Because the minimum SIMD instruction set is SSE2 on IA-32 and SSE3 on Intel 64 processors it is recommended that you ALWAYS call the the ippInit() function before making any other calls to the Intel IPP library. This advice applies regardless of whether you are linking against the static or dynamic form of the library (even though the dynamic library will also perform this call).

Calling the ippInit() function with the shared libraries (DLL and SO) will generate an error message to a dialog box or error console if the ippInit() function detects that the runtime CPU is not supported by the Intel IPP library. Calling the ippInit() function in the static versions of the library will not generate a console or dialog message. Both versions of the ippInit() function will return an error code when a non-supported CPU is detected.

It is important that you call the ippInit() function at the beginning of your application to insure that the processor on which your application is running will support the Intel IPP library. If the ippInit() function returns an error code you should close your application gracefully in order to avoid an unexpected termination of your application by an invalid instruction fault because your application is running on an unsupported processor.

The following table lists the SIMD architecture codes supported by version 7.0 of the Intel IPP library.

For non-Intel based processors support, please read Use Intel® IPP on Intel or Compatible AMD* Processors.

If you compare this dispatch table above to the 5.3 thru 6.1 dispatch table you will note that the Intel SSE3 optimization layer (t7) has been removed from the 32-bit edition (ia32) of the library. 32-bit applications built with the 7.0 version of the library that execute on an SSE3 processor will automatically use the Intel SSE2 optimization layer (w7). In most cases, the impact of this change is minor, since the performance difference between the Intel SSE3 (t7) and Intel SSE2 (w7) optimization layers in the Intel IPP library is minimal. Processors that support the Intel SSSE3 instruction set (v8 and s8 optimization layers) are not affected by this change. (Note: this change does not impact applications built using the 64-bit edition of the library, which now uses the Intel SSE3 optimization layer (m7) as its default path.)

P8/Y8 Internal Run-Time Dispatcher

Within the 32-bit p8 and equivalent 64-bit y8 architectures there is an additional "runtime dispatcher," a mini-dispatcher. The Nehalem and Westmere processor microarchitectures add additional SIMD instructions beyond those defined by SSE4.1. The Nehalem processor microarchitecture added SSE4.2 SIMD instructions and the Westmere processor microarchitecture added Inte® AES-NI.

Creating two separate optimization layers within the IPP library for the small set of instructions added by SSE4.2 and AES-NI would be very space inefficient, so they are bundled into the SSE4.1 library (p8/y8) as minor variants to that optimization layer. When you call a function that includes, for example, AES-NI optimizations, an additional jump directs your call to the AES-NI version within the p8/y8 library if your runtime processor supports these instructions. Because the enhancements affect the optimization of only a small number of Intel IPP functions, this additional overhead occurs infrequently and only when your application is executing on a p8/y8 architecture processor that supports these extra instructions.

S8/N8 (Atom) Dispatch

Unlike preceding versions of the library, the 7.0 version of the Intel IPP library does include Atom-optimized variants of the library within all formats (static and dynamic) of the library. For this reason, the Linux distribution of the 7.0 version of the Intel IPP library no longer includes a separate Atom-specific version of the library, since Atom-specific optimizations have been fully merged into all formats of the standard library files.

Please read Intel® Atom™ Processors Support in the Intel® Integrated Performance Primitives (Intel® IPP) Library for more information regarding Atom optimizations in the IPP library.

Processor Architecture Table

The following table was copied from an Intel Compiler Pro options article describing some compiler architecture options. It contains a list of Intel processors showing which processors support which SIMD instructions. For the latest table please refer to the original article; it gets updated on a regular basis. Please note that the behavior of the Intel Compiler SIMD dispatcher described in that article does not apply to the Intel IPP library.

The Intel IPP library dispatching mechanism behaves differently than that found in the Intel Compiler products, and may also behave differently than other Intel library products.

Additional information regarding dispatching and how it relates to non-Intel processors can be found here. How to identify your specific processor is described here. To correlate a processor family name with an Intel CPU brand name, use the following web site: ark.intel.com.

SSE4.2
Intel® Core™ i7 processors
Intel® Core™ i5 processors
Intel® Core™ i3 processors
Intel® Xeon® 55XX series

SSE4.1
Intel® Xeon® 74XX series
Quad-Core Intel® Xeon 54XX, 33XX series
Dual-Core Intel® Xeon 52XX, 31XX series
Intel® Core™ 2 Extreme 9XXX series
Intel® Core™ 2 Quad 9XXX series
Intel® Core™ 2 Duo 8XXX series
Intel® Core™ 2 Duo E7200

SSSE3
Quad-Core Intel® Xeon® 73XX, 53XX, 32XX series
Dual-Core Intel® Xeon® 72XX, 53XX, 51XX, 30XX series
In tel® Core™ 2 Extreme 7XXX, 6XXX series
Intel® Core™ 2 Quad 6XXX series
Intel® Core™ 2 Duo 7XXX (except E7200), 6XXX, 5XXX, 4XXX series
Intel® Core™ 2 Solo 2XXX series
Intel® Pentium® dual-core processor E2XXX, T23XX series

SSE3
Dual-Core Intel® Xeon® 70XX, 71XX, 50XX Series
Dual-Core Intel® Xeon® processor (ULV and LV) 1.66, 2.0, 2.16
Dual-Core Intel® Xeon® 2.8
Intel® Xeon® processors with SSE3 instruction set support
Intel® Core™ Duo
Intel® Core™ Solo
Intel® Pentium® dual-core processor T21XX, T20XX series
Intel® Pentium® processor Extreme Edition
Intel® Pentium® D
Intel® Pentium® 4 processors with SSE3 instruction set support

SSE2
Intel® Xeon® processors
Intel® Pentium® 4 processors
Intel® Pentium® M

IA32
Intel® Pentium® III Processor
Intel® Pentium® II Processor
Intel® Pentium® Processor

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Note: the library's directory layout changes impact both Windows* and Linux* developers. The examples shown here are for a Windows system.

1. Directories formerly designated as "em64t" are now designated by the "intel64" tag. 
2. Intel IPP shared libraries (*. dll and *.so) have been relocated to a "redist" directory (see diagram below).
3. The OpenMP* libraries and other Intel Compiler redistributable libraries (included with the Intel IPP library) are now located in a common compiler "redist" directory (see diagram below). Note: the static edition of the Intel OpenMP library has been deprecated with this release of the IPP library and should not be used for new projects, please use the shared version of the library.
4. IPP documentation has been relocated to a common directory.
5. Multiple "bin" directories contain utilities to support the development process, such as scripts to set the IPP environment variables.
6. The Intel IPP "lib" directory contains only linkable objects, including the serial static library files, threaded static library files and dynamic stup library files.
7. A new "interface" directory has been introduced with this release. It includes high-level applications and/or libraries that utilize the IPP library. Source and pre-built binaries can be found in these directories and are ready to use in your application.

The following diagram compares the 6.1 directory structure to the 7.0 directory structure:

Note: the "Program Files (x86)" name shown above indicates installation on a 64-bit Windows system. Installation on a 32-bit Windows system alway occurs in the "Program Files" directory.

Note: when installed as part of the Parallel Studio product, the top-level directory containing Intel Composer components (such as the Intel IPP library) includes one additional level and is named: "C:\Program Files\Intel\Parallel Studio xxxx\Composer\" rather than: "C:\Program Files\Intel\ComposerXE-xxxx\" as shown in the diagram above.

Library Filename Changes

Library filenames have also been changed in version 7.0 of the Intel IPP library. The merged/merged_t and emerged static library components have been combined into a single set of files for the serial static library and another set for the threaded static library files. Library filenames ending in an "_l" are single-threaded static libraries and those that end in an "_t" are multi-threaded static libraries. Libraries without postfixes in the name are shared object import libraries. Please see Intel IPP 7.0 - Selecting the Intel(R) IPP Libraries Needed by Your Application for more details.

For example, the following 6.1 link command line:

ippccemerged.lib ippccmerged.lib ippjemerged.lib ippjmerged.lib ippiemerged.lib ippimerged.lib ippsemerged.lib ippsmerged.lib ippcorel.lib

now becomes:

ippcc_l.lib ippj_l.lib ippi_l.lib ipps_l.libippcore_l.lib

when using the Intel IPP 7.0 library.

See also this KB article: Intel® IPP linkage models - quick reference guide.

• Intel IPP Main Product Page
• Intel IPP 6.1 Library Release Notes
• Intel IPP 6.1 Library Installation Guide
• Intel IPP 6.1 Library System Requirements
• Intel IPP 6.1 Library Getting Started
• Intel IPP 6.1 Library Bug Fixes

Links to documentation, help, and code samples can be found on the main Intel IPP product page. For technical support visit the Intel IPP technical support forum and review the articles in the Intel IPP knowledgebase.

Please register your product using your preferred email address. This helps Intel recognize you as a valued customer in the support forum and insures that you will be notified of product updates. You can read Intel's Online Privacy Notice Summary if you have any questions regarding the use of your email address for software product registration.

How to Build an IPP Application provides an introduction to compiling, linking and deploying Intel IPP applications.

Environment Variables

Each platform includes a script (batch file on Windows, shell script on other platforms) in the <install-dir>\tools\env directory that sets the IPPROOT, LIB, INCLUDE and some system-specific environment variables to point to the appropriate IPP install directories. Use of this script is a convenient, but optional, means by which to configure your development system for compiling and linking with the IPP library.

Before running the build scripts provided with any sample IPP applications you must first set the IPPROOT environment variable to point to the IPP installation directory on your system. IPPROOT needs to be configured to point to that directory which contains the bin, lib, include and tools directories. The build scripts will reference the IPPROOT environment variable in order to locate the IPP library and additional scripts.

Once defined, you can reference the IPPROOT variable within your makefiles and/or project files to locate the header and library files necessary to compile and link applications using the Intel IPP library.

On a Windows system the following batch files are available to configure the environment for building IPP applications:

• IA-32 Intel® Architecture: $(IPPROOT)\tools\env\ippenv.bat
• Intel® 64 (Intel® EM64T) Architecture: $(IPPROOT)\tools\env\ippenvem64t.bat
• Intel® Itanium® Architecture: $(IPPROOT)\tools\env\ippenv64.bat

On a Linux system the following shell scripts are available to configure the environment for building IPP applications:

• IA-32 Intel® Architecture: ${IPPROOT}/tools/env/ippvars32.sh
• Intel® 64 (Intel® EM64T) Architecture: ${IPPROOT}/tools/env/ippvarsem64t.sh
• Intel® Itanium® Architecture: ${IPPROOT}/tools/env/ippvars64.sh
• Intel® Atom™ Processor: ${IPPROOT}/tools/env/ippvars32.sh

Include Files

The Intel IPP functions and structures are defined within several header files in the $(IPPROOT)\include directory. The "ipp.h" header file includes all of these. For forward compatibility it is best to include only the ipp.h header file.

Calling Intel IPP Functions

The dynamic library dispatcher and merged static library mechanisms (described below) are designed to make the process of calling an Intel IPP functions as simple as calling any C function. Multiple SIMD-optimized versions of each function are concealed behind a single entry point.

Refer to the documentation for complete descriptions of the Intel IPP functions.

See the following KB articles for more information on linking with the Intel IPP library:

Intel® IPP Linkage Models - Quick Reference Guide
Simplified Link Instructions for the IPP Library

And read these articles for information regarding the IPP dispatching mechanism:

Understanding CPU Dispatching in the Intel® IPP Library
IPP Dispatcher Control Functions - ipp*Init*() Functions

Using the Intel IPP Dynamic (Shared) Libraries

The Intel IPP library includes "stub" static library files that link to the correct entry points and automatically load the appropriate Intel IPP dynamic (shared) libraries at run time. To use the IPP dynamic libraries you must link with the library files located in the $(IPPROOT)\stublib directory.

At run time the dynamic libraries will automatically detect the CPU type and load the correct processor-specific library files. The processor-specific dynamic libraries include suffixes like px, t7, w7, etc. in their names. The only requirements necessary to use the dynamic libraries, once you have linked against the "stub" static libraries, is to insure that they are located in the appropriate system path(s).

Note: the environment scripts described above, in the Environment Variables section, will correctly located your dynamic library files in the appropriate system path(s).

On a Linux system be sure the Intel IPP shared libraries are included in the system variable LD_LIBRARY_PATH. For example, if the libraries are located in the /opt/intel/ipp/6.1.x.xxx/ia32/sharedlib folder, then the following command line should be entered:

export LD_LIBRARY_PATH=/opt/intel/ipp/6.1.x.xxx/ia32/sharedlib:$LD_LIBRARY_PATH

Intel IPP 6.0 and later uses OpenMP to implement it's internal threading. You can use OpenMP environment variables and APIs to control the OpenMP threading behavior. For more information regarding OpenMP and the Intel IPP library, please refer to the following KB articles:

Intel® IPP - Threading / OpenMP* FAQ
OpenMP and the Intel® IPP Library

Note: You must include the appropriate libguide.so (Linux) or libiomp5.dll (Windows) file in your PATH. There are known incompatibilities with other versions of these dynamic libraries. If you encounter problems, make sure that there is only one version located in your PATH.

Please read the following KB articles for information regarding the IPP library processor codes:

Understanding CPU Dispatching in the Intel® IPP Library
IPP Dispatcher Control Functions - ipp*Init*() Functions

Building a Custom Dynamic (Shared) Library

Please see the following KB article and the IPP documentation for information on building a custom dynamic library:

Intel® IPP Linkage Models - Quick Reference Guide

Using the Intel IPP Performance Benchmark Tool

The Intel IPP library includes a tool named "perfsys" to evaluate the performance of each Intel IPP function.
For more details on running perfsys please review the readme.htm file located in the $(IPPROOT)\tools\perfsys directory.

Intel® IPP Library 6.1 Fixes List

The tables below summarize specific customer issues or feature requests that have been addressed by the indicated product releases. Some items span multiple architectures and/or operating systems and some relate only to a single architecture or operating system.

NOTE: The issues, defects, bug reports, and feature requests summarized below represent specific issues with specific test cases. An item listed here does not imply that it necessarily applies to your application(s). If your situation does not match the specific test case you may not have experienced the error or problem associated with that update. It is not possible to describe the details of every issue and its specific test case in these tables.

Providing a complete description of each item in the list below is impractical. For that reason we ask that you post a message on the IPP user forum and reference this page and the "DPD" number of interest if you have further questions regarding the information in these tables. A DPD number with more information has a link.

These tables are updated regularly to correct errors and omissions.

NOTE: The bugs listed below are for both the IPP library and the IPP sample code. Always upgrade the IPP library and sample code at the same time.

IPP v6.1 update 6 (30 Jul 2010)

DPD200155165        UMC simple_player app does not work with Windows Aero interface.
DPD200154198        Data Compression error in ZLIB (deflate.c) when source buffer size >=48K.
DPD200154900        Data compression error with deflate() under certain variable block size conditions.
DPD200153276        Change alignment in H.264 UMC decoder to DECLALIGN macros insted of __ICL alignment.
DPD200087211        Documentation: Example 9-4 ippiFilterColumn() needs to include border information.
DPD200154874        Documentation: ippsFIR() descriptions are misleading or incorrect in description of "numIter" parameter.
DPD200186071        Documentation: Correct example 6-1 using ippiRGBToYUV() -- wrong ROI size: should be {3,3} not {9,3).

IPP v6.1 update 5 (9 Apr 2010)

DPD200150333        Output image has small corruption on top edge when applying WarpAffine with dst roi size (1920 x 240).
DPD200150883        Delphi sample code error on loading file name (sample has been updated).
DPD200089782        JPEG grayscale lossless compresion distortion.
DPD200150199        Error in DIB_PAD_BYTES in UIC picnic sample.
DPD200151794        Corrected results for the ippGetNumCoresOnDie() function on multi-core processors.
DPD200151952        IPP-zlib compress generates spurious compressed data that cannot be decompressed.
DPD200089070        UMC H264EncoderFrameList_InsertFrame() fails allocating 15MB frame buffer, returns null pointer.
DPD200092946        Picnic sample application produces invalid JPEG 2000 files when saving in lossless format.
DPD200187089        ippiRGBToGray_8u_AC4C1R and ippiRGBToGray_8u_C3C1R translate RGB(255,255,255) to 254.
     

IPP v6.1 update 4 (10 Feb 2010)

DPD200149498        Memory leak in H.264 UMC sample code with resolution change on same instance of decoder.
DPD200150122        IPP_BZIP2 data corruption -- data sensitive and isolated to a 3mb fragment of a specific binary file.
DPD200149570        IPP samples redistribution file and EULA updated for clarification.
DPD200087613        ippsFilterNoiseDetect* "ascending noise detection" problem fixed. PESQ was increased by ~0.01.
DPD200148808        Cryptography function ippsECCPComparePoint* contains a misprint: "equial" should be "equal."

IPP v6.1 update 3 (26 Nov 2009)

DPD200140668        ippiResizeSqrPixel_8u_C1R has differing results depending on CPU (rounding error problem)
DPD200134986        DFT performance optimization for lengths 8*n, 16*n, 13*n, p*n (p>50)
DPD200084751        Correct ippiColorToGray_8u_C3C1R rounding errors
DPD200086319        ippiSegmentWatershed_8u16u should use the value IPP_MAX_16U for border pixels but uses 8u instead
DPD200084408        Problem with IPP linking in kernel mode for Intel64 (em64t red zone in ring0 and interrupts)
DPD200087170        ippiCopy_8u_C1R performance on v8 architecture (v8 code slower in Core 2 Duo than t7 and w7)
DPD200141560        Feature request: BZIP2 with ipp_ prefixes

IPP v6.1 update 2 (18 Oct 2009)

DPD200084538        UIC sample picnic.exe (64 bits) cannot be started
DPD200085298        Linking problem on 64-bit Mac OS X with IPP fuctions
DPD200084177        Image artifacts in jpeg2000 image
DPD200140266        DMIP crashes when reusing graphs
DPD200140194        BWT error
DPD200138989        Running application in debug causes heap corruption at the end of functions that use UIC classes
DPD200133386        mp3 encoder produces fuzzy results with 8k sampleing rate PCM
DPD200136808        IPP C# wrapper bugs
DPD200134685        ippiAbs_32f_AC4IR failed with 300x300
DPD200134689        C++ sample ippi.hpp missing ippiCopy_16u_C1R
DPD200134691        Remove description of ippiGrayDilateBorder/ippiGrayErodeBorder
DPD200132032        ROI is reversed in ippiResizeSqrPixel_x_P
DPD200132261        Fix the jpegview makefile for OpenMP from MS VC.NET 2005
DPD200128941        Small destination block size optimization
DPD200132721        Crypto sample error: add -lguide -lpthread in build_ssl_ipp.sh
DPD200133648        ippiSwapChannels_8u_C41R crashes with small image width
DPD200133653        OverFlow in 10-bit DCT ippiDCT8x8Inv_16s_C11()
DPD200134288        Bug in WarpBilinearBack function with NN interpolation
DPD200134697        Problem with ippiFilterGaussBorder_32f_C1R
DPD200133374        Correction to custom DLL section of the User Guide
DPD200133665        Document: Output for example 12-27 in ippsman.pdf is incorrect
DPD200134755        Incorrect decoding for IPP MJPEG sample in UMC
DPD200130124        JPEG color conversion functions
DPD200133693        Line 741 of umc_frame_constuctor.cpp
DPD200134726        Document error: ippiMirror returns ippStsSizeErr
DPD200134712        Distored JPEG output
DPD200134959        Unexpected result with ippiColorToGray with integer inputs
DPD200134967        UMC::ColorSparceConversion YUY2->YV12 error
       

IPP v6.1 update 1 (02 Jul 2009)

DPD200133747        ippiForegroundGaussian does not produce expected results
DPD200134979        ResizeSqrPixel function crash when size<=6
DPD200133708        ippiResizeSqrPixel_8u_C1R performance issue
DPD200132114        ippiQualityIndex_16u32f_C3R() error
DPD200131846        Inconsistent use of const specifier for some IPP functions
DPD200133631        Improve scripts to display clear error message
DPD200131102        No explanation of nonpic libs (linux) in documentation
DPD200134358        NHM (Intel Nehalem microarchitecture) function optimizations
DPD200133920        ippsFIRSparse is slower than using SSE compiler intrinsics
DPD200134752        Incorrect conversion of RGB to Gray
DPD200134693        redist.txt missing ipp*merged_t.lib
DPD200134748        Redistribute and document libmmds.lib
DPD200134969        Gather interface for accumlulating AAD for AES-GCM
DPD200136077        Sample build problem: file not found: libiomp5.dylib
DPD200082620        G711 bug in PLC
DPD200134973        UMC::ColorSpaceConversion YUY2 -> YV12 error
DPD200134862        Bug in umc_video_processing.cpp
DPD200134779        ippsCIS_32fc_All does not work
DPD200134356        IPP ZLIB fails to compress image after gzrewind
DPD200134270        ippiNormDiff_L1_8u_C1R error
DPD200133638        ippsNorm_L1_16s32f bug
DPD200132645        MPEG4 decoding problem
DPD200132341        Makefile error for UMC
DPD200131704        Resize function error
DPD200131142        ippiUndistortRadial function gives wrong results
DPD200130292        Performance issue for ippsAccCovarianceMatrix_32f64f_D2
DPD200130035        Add notes for ippiDCTQuantInv8x8LS_JPEG_16s16u functions
DPD200133943        Improve MPEG2Mux
DPD200133939        IppiCrossCorrValid_NormLevel_8u32f
DPD200130294        Performance issue for IPP String processing function on EM64T systems
DPD200134815        ippsResamplePolyphase_32f performance issue
DPD200134750        Internal function cpMul_BNU_FullSize does not obey the IPF software conventions
DPD200134716        ippiCrossCorrFull_NormLevel gives unexpected results
DPD200134707        Crash inside ippiInterpolateAverage16x16_8u_C1IR
DPD200133569        Intermediate computational errors
DPD200129130        Wiener filter MaskSize error
DPD200129122        2D media filter performance
DPD200134399        Incorrect Redist.txt file
DPD200134254        Modify IPP ZLIB sample to get better performance
DPD200128923        Watershed segmentation for 32 bit float images added
DPD200134378        Crypto sample does not work with latest OpenSSL package
DPD200133670        Problems encoding 16u_C1 jpeg2000
DPD200130345        Add destructive versions of ippsNthMaxElement_32f_I

IPP v6.1 (25 Apr 2009)

DPD200134199        Feature request: Improve the UMC sample code buiding script
DPD200134679        V-plane Corrupted when input 640x480 YUV422 into encoder
DPD200134370        Bug in 'ippiRGBToYCbCr_8u_C3R'
DPD200134362        ippiTrueDistanceTransform_8u32f_C1R caps the maximum distance value at 1000.0
DPD200134360        ippiDecodeHuffman8x8_Direct_JPEG_1u163_C1 reads beyond input data
DPD200134387        Cannot use libipp_z.a and libipp_bzip2.a at the same time
DPD200134597        Error in color conversion function 'ippiRGBToYCbCr420_8u_C3P3R' for 'u8' variant
DPD200134372        Read error in 'ippiDCTQuantInv8x8To2x2LS_JPEG_16s8u_C1R' for JPEG decoding
DPD200134341        'ippiCompColorKey_8u_C4R' does not work correctly for some ROI widths
DPD200134447        Remove ippStaticInitBest() from Getting_started.htm
DPD200134092        IPP-Crypto- support to RSA_SSA1.5 nor RSA_PKCSv1.5
DPD200133906        ippiCrossCorrValid_NormLevel_32f_C1R on EM64T system
DPD200134376        Bug in colors for planar destinations at lower resolution option in 'JPEGView'
DPD200134386        Issue with ippiTrueDistanceTransform_8u32f_C1R function
DPD200133691        A number of UMC MPEG-4 decoder issues (IPP v. 5.2)
DPD200134366        Missing build64.sh file from data compression sample
DPD200133646        ippsRandomRunform_8u does not produce the upper border value
DPD200133366        Resolution not saved in jpeg
DPD200134179        ippGetStatusString crash in C# sample code
DPD200133821        USC_EC delay issues
DPD200134368        Bug in the state of CABAC in that mode
DPD200133819        Add pixel aspect ratio as a configuration parameter
DPD200134284        Add info about RTI removal to the release notes
DPD200133689        A number of issues for the H.264 UMC decoder
DPD200134397        H264 encoder problem after running many hours
DPD200134487        UMC H264 parser memory leak