This document provides a general summary of new features and important notes about the Intel® IPP library software product.

Please see the following links for the latest information regarding the Intel® Integrated Performance Primitives (Intel® IPP):

• Intel® IPP Main Product Page
• Intel® IPP 7.0 Release Notes
• Intel® IPP 7.0 Installation Guide
• Intel® IPP 7.0 System Requirements
• Intel® IPP 7.0 Getting Started
• Intel® IPP 7.0 Bug Fixes

Links to documentation, help, and code samples can be found on the main Intel IPP product page. For technical support visit the Intel IPP technical support forum and review the articles in the Intel IPP knowledgebase.

Please register your product using your preferred email address. This helps Intel recognize you as a valued customer in the support forum and insures that you will be notified of product updates. You can read Intel's Online Privacy Notice Summary if you have any questions regarding the use of your email address for software product registration.

How to Build an IPP Application provides an introduction to compiling, linking and deploying Intel IPP applications.

What's New in Intel® IPP 7.0

• Additional optimizations for the 256-bit Intel AVX SIMD instruction set.
• Further AES-NI optimizations for cryptography and data compression.
• Microsoft* Visual Studio* 2010 support.
• A JPEG-XR (HD Photo) codec is now included in the UIC framework.
• A Windows Imaging Codec (WIC) has been added to the UIC sample.
• The new interfaces directory contains high-level application code, in the form of source and pre-built binaries.
• A New Directory Structure and Library Naming Scheme describes library layout and name changes important to developers.

A complete list of new functions added with the 7.0 release is located in the NewFunctionsList.txt file, which can be found in the ...\Documentation\en_US\ipp\ directory. You will also find the ThreadedFunctionsList.txt file in that same location, listing those functions that are available in an internally threaded format. Threading, within the multi-threaded variants of the Intel IPP library, is accomplished by use of the Intel® OpenMP* library.

For a more detailed list of what's new in Intel IPP 7.0 please read this article.

7.0 update 7 Release Notes

• An OpenGL video renderer has been added to Microsoft* Windows* audio-video-codecs (UMC). To enable, uncomment "#define UMC_ENABLE_NEW_RENDERS" in core/umc/include/umc_defs.h. See simple_player readme for more details. Note: Building UMC in a new directory is recommended. If your build process copies over a previous version of UMC, please remove null_drv.c, null_drv.h, null_video_renderer.cpp, and null_video_renderer.h from io/video_renders.
• Multiple bug fixes have been incorporated. See the KB article titled Intel® IPP 7.0 Library Bug Fixes for details.

7.0 update 6 Release Notes

• The ippiDCTFwd_32f_C1R function was threaded for additional performance improvement.
• Multiple bug fixes have been incorporated. See the KB article titled Intel® IPP 7.0 Library Bug Fixes for details.

7.0 update 5 Release Notes

For technical reasons related to installation packaging, two editions of the 7.0.5 release have been issued. The Intel IPP library product binaries contained within these two 7.0.5 installation packages are identical. If you install the cryptography package make sure the three digit product ID on the install file (e.g. w_ccompxe_crypto_ipp_7.0.5.258.zip) matches the three digit ID in the main install package filename (e.g. w_ipp_7.0.5.258_ia32.exe).

• The ippiDCTFwd_32f_C1R function was optimized more than 2x speedup
• Multiple bug fixes have been incorporated. See the KB article titled Intel® IPP 7.0 Library Bug Fixes for details.

7.0 update 4 Release Notes

For technical reasons related to installation packaging, two editions of the 7.0.4 release were issued. The Intel IPP library product binaries contained within these two 7.0.4 installation packages are identical. If you install the cryptography package make sure the three digit product ID on the install file (e.g. w_ccompxe_crypto_ipp_7.0.4.221.zip) matches the three digit ID in the main install package filename (e.g. w_ipp_7.0.4.221_ia32.exe).

• The px_/mx_ prefixes have been restored to the static generic library so that you can now include the static generic library in the same application that includes the product library. The automatic dispatcher will not recognize the generic library and will not dispatch to the generic optimizations; instead, you must call the generic functions directly with the px_/mx_ prefix. For more information, please see the KB article titled Generic Static Library Dispatching with the Intel® IPP 7.0 Library.
• Multiple bug fixes have been incorporated. See the KB article titled Intel® IPP 7.0 Library Bug Fixes for details.

7.0 update 3 Release Notes

• Additional optimizations for the Intel® Atom™ instruction set have been incorporated. Please review the KB article titled Intel® Atom™ Processor support in the Intel® Integrated Performance Primitives (Intel® IPP) Library for details regarding which functions include direct optimization for the Intel Atom processor.
• Multiple bug fixes and performance enhancements have been incorporated, especially relating to the UMC sample.

7.0 update 2 Release Notes

• Additional optimizations for the 256-bit Intel® AVX SIMD instruction set have been incorporated. Please review the KB article titled Intel® IPP Functions Optimized for Intel® AVX (Intel® Advanced Vector Extensions) for details regarding which functions include direct optimization for the Intel AVX instructions.
• New optimizations for the Intel® Atom™ instruction set have been incorporated. Please review the KB article titled Intel® Atom™ Processor support in the Intel® Integrated Performance Primitives (Intel® IPP) Library for details regarding which functions now include direct optimization for the Intel Atom processor.
• Data compression Huffman performance gains of about 2x achieved via a redesign of the "Inflate for Fixed Huffman" algorithm.
• Cryptography improvements include 1.4x faster "sign verify" and a 2x faster ippsMontForm() function. In addition, improvements have been made to the ippsDLPSignDSA(), ippsDLPVerifyDSA(), ippsDLPGenKeyPair() and ippsDLPPublicKey() functions.
• The ipp_zlib library has been updated so it is now based on the zlib 1.2.5 distribution.

7.0 update 1a Release Notes

For technical reasons related to installation packaging, two editions of the 7.0.1 release have been issued. The Intel IPP library product binaries contained within these two 7.0.1 installation packages are identical. The second edition adds legacy px/mx "generic" add-on libraries for use in those situations where the new minimum SSE base level (see "7.0 update 1 Release Notes" below) will not work for your target systems.

IMPORTANT: Most systems do not require these add-on generic libraries! It is not necessary to download and re-install this edition of the Intel IPP library on your development system if you have already successfully downloaded and installed the first edition of the 7.0.1 library, either as a standalone product or as part of one of the Intel® Parallel Studio XE or Intel® Composer XE products.

These generic add-on libraries contain 32-bit and 64-bit code in single-threaded static and multi-threaded dynamic format only. The generic dynamic library files will automatically integrate with the Intel IPP library dispatch mechanism; the generic static library files do not integrate with the Intel IPP dispatcher.

Since the generic add-on libraries are provided in standard archives, you install them manually (as you currently do with the Intel IPP samples). If you have already installed the first edition of 7.0.1 on your system you do not need to download and re-install the entire 7.0.1a package; instead, download only the generic add-on library archives and extract the library files from those archives into their respective locations in your existing Intel IPP installation directories.

• 1st edition Windows 7.0.1 files are denoted with a 7.0.1.104 or 7.0.1.041 label.
• 2nd edition Windows 7.0.1a files are denoted with a 7.0.1.127 or 7.0.1.046 label.
• 1st edition Linux 7.0.1 files are denoted with a 7.0.1.084 or 7.0.1.029 label.
• 2nd edition Linux 7.0.1a files are denoted with a 7.0.1.107 or 7.0.1.037 label.

7.0 update 1 Release Notes

• Additional optimizations for the 256-bit Intel® AVX SIMD instruction set (available on Intel® processors conforming to the Sandy Bridge microarchitecture) have been incorporated. Please review the KB article titled Intel® IPP Functions Optimized for Intel® AVX (Intel® Advanced Vector Extensions for more information about which functions include optimizations for the Intel AVX instructions.
• IMPORTANT! The Intel SSE3 optimization layer (t7) has been removed from the 32-bit edition (ia32) of the library and
the minimum SIMD instruction level supported by this version of the library has changed. Please review the article titled Understanding SIMD Optimization Layers and Dispatching in the Intel IPP 7.0 Library for more information.

7.0 Release Notes

The initial release of the Intel IPP library was only distributed as part of the Intel® Parallel Composer 2011 product, which is distributed with the Intel® Parallel Studio 2011 product, and is only available for the Microsoft* Windows* platform. Update releases are available on all supported platforms and as standalone products.

Performance and Optimization Changes:

• Additional optimizations for the 256-bit AVX SIMD instruction set (available on Intel® processors conforming to the Sandy Bridge microarchitecture) have been incorporated.
• AVX optimization (g9/e9) is enabled by default; eliminating the requirement to use ippEnableCpu() on AVX capable processors.
• Further AES-NI optimizations have been applied to the cryptography domain (separate download, see below) and data compression (CRC32 for ipp_bzip2), substantially improving performance on those processors that support the AES-NI instructions.
• Intel® Itanium® architecture (IA-64) support is not included in this release of the library. Intel IPP 6.1 is the latest release for the IA-64 architecture.
• The base 32-bit optimization layer of the library (px) has been compiled for higher performance and now requires a processor that conforms to the SSE2 processor architecture; this change is consistent with the requirements of the 64-bit base optimization layer (mx).
• The standalone Intel Atom™ processor static libraries have been merged into the dispatched versions of the static library.
• The SSE2 optimization layers (t7/m7) have been removed from this version of the IPP library; they will continue to be supported in the Intel IPP 6.1 product.
• The 32-bit SSE3 optimization layer (w7) has been removed from this version of the IPP library; it continues to be supported in the Intel IPP 6.1 product.
• New ippSetAffinity() function provides finer control of OpenMP threading within the library. For a complete list of threaded functions, please review the ThreadedFunctionsList.txt list located in the Intel IPP documentation directory.
• ippInitCpu() now provides finer grained control over internal library dispatching for Intel processors conforming to the Penryn, Nehalem, and Westmere microarchitectures.
• The OpenMP static library has been deprecated; all IPP samples now reference only the OpenMP dynamic/shared library.
• The AES GCM API has been augmented to improve performance of AES encryption on pre-Westmere CPUs.

Microsoft* Visual Studio* Support:

• Microsoft* Visual Studio 2010 is now supported by the Windows edition of the Intel IPP library; meaning, Intel IPP library help files and project files are now compatible with the Visual Studio 2010 IDE. The Visual Studio 2005 and 2008 IDEs continue to be supported. Visual Studio .NET (2003) help is not supported by this release of the library; however, Intel IPP 7.0 applications can still be compiled and linked using the VS.NET IDE.
• The DMIP sample now includes a Microsoft* DSL (Domain Specific Language) add-on for use with Microsoft* Visual Studio 2008.

Domain-Specific Changes:

• Many new functions have been added to the library API in this release of the product, including IPPI_ANTIALIASING mode support for ippiResizeSqrPixel, new color conversion functionality for JPEG image processing and additional context functionality for the cryptography domain. For a complete list of the new functions added to this release please see the NewFunctionsList.txt list located in the Intel IPP documentation directory.
• Support for the JPEG-XR (HD Photo) forward and inverse transforms for 16s, 32s and 32f data types and variable length code (VLC) encode and decode functions for 32s data types has been added.
• A JPEG-XR (HD Photo) codec is now included in the UIC sample framework for grayscale, RGB and RGBA images with 8, 16, and 32-bit integer and 16 and 32-bit floating point pixel depths.
• A new Windows Imaging Codec (WIC) added to the UIC sample.
• The matrix math domain adds 86 new 3D math functions designed for use with the Microsoft* DirectX API. A DirectX compatible sample using these functions is also provided, making it very easy to integrate these functions into existing DirectX applications.
• The speech recognition functions (ippSR domain) are not part of this release; this domain will continue to be supported in the IPP 6.1 product.
• The SPIRAL generated functions (ippGEN domain) are now distributed as a separate download. See instructions below for more information.
• The UMC simple_player application now runs on the Windows* Vista* and Windows 7* Aero interface.

New High-Level APIs:

• A new interfaces directory has been added that contains high-level application code, in the form of source and pre-built binaries. Several popular data compression libraries (e.g., bzip2, zlib and gzip) have been modified for use with the Intel IPP library and can be found in this new interfaces directory for immediate use in your applications.
• There is a new ipp_lzopack (data compression) library, located in the interfaces directory mentioned above.
• Multi-threading is now part of the ipp_zlib library (by use of the OpenMP multi-threading library), also located in the new interfaces directory.

Installation Changes:

• Documentation is now delivered in searchable HTML format; Windows CHM and Adobe PDF formats have been removed.
• A new directory hierarchy has been established to simplify integration of the Intel IPP library with Intel Compiler products. This change may require updates to existing build scripts, makefiles and/or Visual Studio project files.
• Directories formerly designated as "em64t" are now designated with the "intel64" tag. This change may require changes to existing build scripts, makefiles and/or Visual Studio project files.
• Library filenames have been normalized to be consistent between 32-bit and 64-bit architectures (i.e., the "em64t" tag has been removed from all 64-bit library file names). This change may require that you update your build scripts, makefiles and/or Visual Studio project files.
• The domain-specific "emerged" and "merged" static library files have been combined (e.g., ippsemerged.lib + ippsmerged_t.lib ? ipps_t.lib) for simpler reference and the single-threaded static libraries are now designated by a "_l" suffix (multi-threaded static libraries continue to be designated by a "_t" suffix). This change may require updates to existing build scripts, makefiles and/or Visual Studio project files.
• The OpenMP static libraries have been deprecated; these OpenMP library components will still be shipped as part of this version of the product, but will be removed in a future release. See the Intel Compiler documentation for more information regarding OpenMP.

Product Contents

The core Intel® Integrated Performance Primitives (Intel® IPP) v7.0 for Microsoft* Windows* consists of two installation packages:

• Intel® IPP for Microsoft* Windows* on IA-32 Intel® Architecture
• Intel® IPP for Microsoft* Windows* on Intel® 64 Architecture

and the following optional add-on packages:

• Intel® IPP for Microsoft* Windows* Crypography Add-on
• Intel® IPP for Microsoft* Windows* SPIRAL Add-on
• Intel® IPP for Microsoft* Windows* Samples

The core Intel® Integrated Performance Primitives (Intel® IPP) v7.0 for Linux* consists of two installation packages:

• Intel® IPP for Linux* on IA-32 Intel® Architecture
• Intel® IPP for Linux* on Intel® 64 Architecture

and the following optional add-on packages:

• Intel® IPP for Linux* Crypography Add-on
• Intel® IPP for Linux* SPIRAL Add-on
• Intel® IPP for Linux* Samples

There is no standalone installation of the Intel IPP v7.0 for Mac OS X*. The Intel IPP 7.0 for Mac OS X is distributed as part of the Intel® Composer XE and Intel® C++ Composer XE product suites.

Intel® IPP for Cryptography is a Separate Download

The Intel IPP for cryptography is a separate installation package that contains the binaries and header files needed to utilize the functions contained in the Intel IPP cryptography domain. It is an add-on to the Intel IPP library and, therefore, requires that the core Intel IPP already be installed on your system. You must first install the standalone Intel® IPP, Intel® Cluster Studio XE, Intel® C++ Studio XE, Intel® Composer XE, Intel® Parallel Composer, Intel® Parallel Studio, or the Intel® Parallel Studio XE product before installing the respective Intel IPP for cryptography package.

To obtain the Intel IPP for cryptography, which are distributed separately from the main Intel IPP, review this knowledge base article: Where do I download the Intel IPP for Cryptography?.

Intel® IPP SPIRAL Domain (ippGEN) is a Separate Download

In order to decrease the size of the Intel IPP installation package, the SPIRAL subset (ippGEN) of the signal processing domain is now distributed as a separate library add-on. Go to the Intel Registration Center to download the ippGEN component of the Intel® IPP.

SPIRAL for Intel® IPP is a separate installation package that contains the binaries and header files needed to utilize the functions contained in the ippGEN domain. It is an add-on to the Intel® IPP and, therefore, requires that the core Intel® IPP be already installed on your system. You must first install the standalone Intel® IPP, Intel® Cluster Studio XE, Intel® C++ Studio XE, Intel® Composer XE, Intel® Parallel Composer, Intel® Parallel Studio, or the Intel® Parallel Studio XE product before installing the respective SPIRAL add-on library.

The ippGEN package is an adjunct to the ippSP (Signal Processing) domain. It contains signal processing functions that have been optimized for non-ordinary size data sets, primarily in the class of FFT functions. If you have not used these "ippg" functions in the past it is likely that you do not need to download and install this add-on library. However, there is no harm to installing this add-on with the core Intel IPP.

Technical Support

If you did not register your Intel software product during installation, please do so now at the Intel® Software Development Products Registration Center. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For technical information about the Intel IPP, including FAQ's, tips and tricks, and other support information, please visit the Intel® IPP forum: http://software.intel.com/en-us/forums/intel-integrated-performance-primitives/ and browse the Intel® IPP knowledge base: http://software.intel.com/en-us/articles/intel-ipp-kb/all/.

For general information about Intel technical support, product updates, user forums, FAQs, tips and tricks and other support questions, please visit http://www.intel.com/software/products/support/.

Note: If your distributor provides technical support for this product, please contact them rather than Intel.

License Definitions

Any software source code included with this product is furnished under a software license and may only be used or copied in accordance with the terms of that license. Please see the Intel Software Products End User License Agreement for license definitions and restrictions on the library.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to http://www.intel.com/design/literature.htm.

The Intel IPP library functions may contain code that can be used for implementations of algorithms that may require complying with patent conditions.

Please be aware that the RC5 algorithms are patented by Rivest, Ronald L.; RSA* Data Security, Inc. US patent 5,724,428.

Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. For a complete list of Intel trademarks please go here: http://www.intel.com/sites/sitewide/en_US/tradmarx.htm.

*Other names and brands may be claimed as the property of others.

Copyright © 2002-2012, Intel Corporation. All rights reserved.

Hand-tuned optimizations designed to maximize performance of the Intel IPP library on Intel Atom processors were added beginning with v6.0 of the Intel IPP library. For maximum performance on Intel Atom processors, we recommend that you upgrade to version 7.0 of the Intel IPP library.

Both static and dynamic/shared libraries in v7.0 of the Intel IPP library include Intel Atom processor optimizations. Applications linked with versions 7.0 of the Intel IPP library will be dispatched to the "s8" optimized library for IA-32 and the "n8" library for Intel® 64 whenever your application executes on an Intel Atom processor.

For more information regarding dispatching please see Understanding CPU Dispatching in the Intel® IPP Library or check the Intel IPP Getting_Started.htm and userguide_*.pdf files in the Intel IPP documentation.

In the v6.x Intel IPP library, only the dynamic/shared libraries contain Intel Atom processor optimizations; there are no Intel Atom processor optimizations in the v6.x dispatched static libraries. However, the v6.x dispatched static libraries will safely run on an Intel Atom processor by dispatching to the v8/u8 libraries optimized for the Merom microarchitecture (Intel Core 2 processor), which is also designed for use with the same Intel Supplemental SSE3 SIMD instruction set (SSSE3) that Intel Atom processors support. A separate non-dispatched static Intel IPP library for Linux* is available on the IA-32 platform (and as part of the Intel Atom SDK).

The following list of functions have been hand-optimized for the Intel Atom processor for the version of the Intel IPP library listed at the beginning of this article.

Note: every Intel IPP library primitive is available for use with the Intel Atom processor, this list simply shows those functions which have been specially hand-tuned for the Intel Atom processor; hand-tuning is not required to achieve optimum performance for all IPP functions. If you have some specific Intel IPP functions that are not listed in the following table, and would like to see them added to the priority list for Atom optimization, please create a thread on the IPP forum stating which functions you would like to see added to the Atom optimization priority list.

ippsAddProduct_32f
ippsAddProduct_32fc
ippsAddProduct_32s_Sfs
ippsAddProduct_64f
ippsAddProduct_64fc
ippsAdd_32f    
ippsAdd_32fc   
ippsAdd_64f    
ippsAdd_64fc
ippsAdd_32f_I
ippsAdd_32fc_I
ippsAdd_32s_Sfs
ippsConvert_16s32f
ippsConvert_16u32f
ippsConvert_32f16s_Sfs
ippsConvert_32f16u_Sfs
ippsConvert_32f32s_Sfs
ippsConvert_32f8s_Sfs
ippsConvert_32f8u_Sfs
ippsConvert_32s32f
ippsConvert_32s64f
ippsConvert_64f32s_Sfs
ippsConvert_8s32f
ippsConvert_8u32f
ippsCopy_16s
ippsCopy_64s
ippsDFTFwd_CToC_32fc
ippsDFTFwd_CToC_64fc
ippsDiv_16sc_Sfs
ippsDiv_16s_Sfs
ippsDiv_16u_Sfs
ippsDiv_32f
ippsDiv_32fc
ippsDiv_32s16s_Sfs
ippsDiv_32s_Sfs
ippsDiv_64f
ippsDiv_64fc
ippsDotProd_32f32fc64fc
ippsDotProd_32f64f
ippsDotProd_32fc64fc
ippsDotProd_64f
ippsDotProd_64f64fc
ippsDotProd_64fc
ippsFFTFwd_CToC_32fc
ippsFFTFwd_CToC_64fc
ippsFilterMedian_32f
ippsFilterMedian_32s
ippsFilterMedian_64f
ippsFIR32f_16s_Sfs
ippsFIR64f_16s_Sfs
ippsFIR64f_32s_Sfs
ippsFIR_32f
ippsFIR_64f
ippsJoin_32f16s_D2L
ippsLShiftC_32s_I
ippsMax_32s
ippsMean_32f
ippsMin_32s
ippsMul_32f       
ippsMul_32fc      
ippsMul_64f       
ippsMul_64fc
ippsMul_32f_I
ippsMulC_32f
ippsMulC_32f_I
ippsNorm_L2_32f
ippsNormDiff_L2_32f
ippsRShiftC_32s_I
ippsSampleUp_32f
ippsScale_32f_I
ippsSqr_32f
ippsSqr_32f_I
ippsSqr_32fc
ippsSqr_64f
ippsSqr_64fc
ippsSqrt_16s_Sfs
ippsSqrt_16u_Sfs
ippsSqrt_32f
ippsSqrt_32f_I
ippsSqrt_32fc
ippsSqrt_64f
ippsSqrt_64fc
ippsSub_32s_Sfs
ippsSub_32f       
ippsSub_32f_I
ippsSub_32fc      
ippsSub_64f       
ippsSub_64fc      
ippsSum_32f
ippsSum_32f
ippsThreshold_LTVal_32f_I

ippsAdaptiveCodebookSearch_RTA_32f
ippsSBADPCMEncode_G722_16s
ippsSBADPCMDecode_G722_16s
ippsDCTFwd_G7221_16s
ippsDCTInv_G7221_16s
ippsDecomposeDCTToMLT_G7221_16s
ippsDecomposeMLTToDCT_G7221_16s
ippsEnvelopFrequency_G7291_16s
ippsFilterHighpass_G7291_16s
ippsFilterLowpass_G7291_16s
ippsFIRSubbandLow_EC_32sc_Sfs
ippsFIRSubbandLowCoeffUpdate_EC_32sc_I
ippsFixedCodebookSearch_RTA_32f
ippsFixedCodebookSearchRandom_RTA_32f
ippsLSPToLPC_RTA_32f
ippsLSPQuant_RTA_32f
ippsMDCTFwd_G7291_16s
ippsMDCTPostProcess_G7291_16s
ippsQMFDecode_G722_16s
ippsQMFDecode_G7291_16s
ippsQMFEncode_G722_16s
ippsQMFEncode_G7291_16s
ippsSubbandAnalysis_16s32sc_Sfs
ippsSubbandController_EC_32f
ippsSubbandControllerUpdate_EC_32f
ippsSubbandSynthesis_32sc16s_Sfs
ippsTiltCompensation_G7291_16s
ippsToeplizMatrix_G729_32f
ippsToneDetect_EC_32f

ippsCRC32_8u
ippsEncodeRLE_BZ2_8u
ippsReduceDictionary_8u_I
ippsVLCCountBits_16s32s
ippsVLCDecodeOne_1u16s
ippsVLCDecodeUTupleBlock_1u16s
ippsVLCDecodeUTupleOne_1u16s
ippsVLCEncodeInit_32s

ippsMDCTInvWindow_MP3_32s
ippsPow43Scale_16s32s_Sf
ippsPow43_16s32f
ippsPredictCoef_SBR_C_32fc_D2L
ippsSynthesisDownFilter_SBR_CToR_32fc32f_D2L
ippsSynthesisDownFilter_SBR_RToR_32f_D2L
ippsSynthesisFilter_PQMF_MP3_32f
ippsSynthesisFilter_SBR_CToR_32fc32f_D2L
ippsSynthesisFilter_SBR_RToR_32f_D2L
ippsVLCDecodeEscBlock_AAC_1u16s
ippsVLCDecodeEscBlock_MP3_1u16s
ippsVLCDecodeUTupleEscBlock_AAC_1u16s
ippsVLCDecodeUTupleEscBlock_MP3_1u16s

ippiAdd_16s_C1IRSfs
ippiConvert_16u32f_C1R 
ippiConvert_16u8u_C3R 
ippiConvert_8u16s_C1R
ippiConvert_8u16u_C1R 
ippiCopyReplicateBorder_16s_C1R
ippiCopy_8u_C1R 
ippiCopy_8u_C3R 
ippiCopy_8u_C4R 
ippiDilate_32f_AC4R 
ippiDilate_32f_C1R 
ippiDilate_32f_C3R 
ippiDiv_16s_AC4RSfs 
ippiDiv_16s_C1RSfs 
ippiDiv_16s_C3RSfs 
ippiDiv_16s_C4RSfs 
ippiDiv_16u_AC4RSfs 
ippiDiv_16u_C1RSfs 
ippiDiv_16u_C3RSfs 
ippiDiv_16u_C4RSfs 
ippiDiv_32f_AC4R 
ippiDiv_32f_C1R 
ippiDiv_32f_C3R 
ippiDiv_32f_C4R 
ippiErode_32f_AC4R 
ippiErode_32f_C1R 
ippiErode_32f_C3R 
ippiFilter32f_8u_AC4R
ippiFilter32f_8u_C1R 
ippiFilter32f_8u_C3R 
ippiFilter32f_8u_C4R 
ippiFilterGauss_16s_AC4R 
ippiFilterGauss_16s_C1R 
ippiFilterGauss_16s_C3R 
ippiFilterGauss_16s_C4R 
ippiFilterGauss_32f_AC4R 
ippiFilterGauss_32f_C1R 
ippiFilterGauss_32f_C3R 
ippiFilterGauss_32f_C4R 
ippiFilter_16s_AC4R 
ippiFilter_16s_C1R 
ippiFilter_16s_C3R 
ippiFilter_16s_C4R 
ippiFilter_16u_AC4R 
ippiFilter_16u_C1R 
ippiFilter_16u_C3R 
ippiFilter_16u_C4R 
ippiFilter_8u_AC4R 
ippiFilter_8u_C1R 
ippiFilter_8u_C3R 
ippiFilter_8u_C4R 
ippiGetPerspectiveQuad
ippiMirror_16u_C1IR
ippiMirror_16u_C4R 
ippiMirror_32s_C4R 
ippiMirror_8u_C4R 
ippiMul_32f_AC4R 
ippiMul_32f_C1R 
ippiMul_32f_C3R 
ippiMul_32f_C4R 
ippiSet_16u_C3R 
ippiSet_16u_C4R 
ippiSet_32f_C1R 
ippiSet_32f_C3R 
ippiSet_8u_C3R 
ippiSet_8u_C4R 
ippiSqrt_16s_AC4RSfs 
ippiSqrt_16s_C1RSfs 
ippiSqrt_16s_C3RSfs 
ippiSqrt_16u_AC4RSfs 
ippiSqrt_16u_C1RSfs 
ippiSqrt_16u_C3RSfs 
ippiSqrt_32f_AC4R 
ippiSqrt_32f_C1R 
ippiSqrt_32f_C3R 
ippiSqr_32f_AC4R 
ippiSqr_32f_C1R 
ippiSqr_32f_C3R 
ippiSqr_32f_C4R 
ippiSub_16s_C1IRSfs

ippiBGR555ToYCbCr420_16u8u_C3P3R
ippiBGR555ToYCbCr422_16u8u_C3C2R
ippiBGR555ToYCbCr422_16u8u_C3P3R
ippiBGR555ToYCrCb420_16u8u_C3P3R
ippiBGR555ToYUV420_16u8u_C3P3R
ippiBGR565ToYCbCr411_16u8u_C3P3R
ippiBGR565ToYCbCr420_16u8u_C3P3R
ippiBGR565ToYCbCr422_16u8u_C3C2R
ippiBGR565ToYCbCr422_16u8u_C3P3R
ippiBGR565ToYCrCb420_16u8u_C3P3R
ippiBGR565ToYUV420_16u8u_C3P3R
ippiBGRToCbYCr422_8u_AC4C2R
ippiBGRToHLS_8u_AC4P4R
ippiBGRToHLS_8u_AP4C4R
ippiBGRToHLS_8u_AP4R
ippiBGRToHLS_8u_C3P3R
ippiBGRToHLS_8u_P3C3R
ippiBGRToHLS_8u_P3R
ippiBGRToYCbCr422_8u_AC4C2R
ippiBGRToYCbCr422_8u_AC4P3R
ippiBGRToYCbCr422_8u_C3C2R
ippiBGRToYCbCr422_8u_C3P3R
ippiCbYCr422ToBGR_8u_C2C4R
ippiHLSToBGR_8u_AC4P4R
ippiHLSToBGR_8u_AP4C4R
ippiHLSToBGR_8u_AP4R
ippiHLSToBGR_8u_C3P3R
ippiHLSToBGR_8u_P3C3R
ippiHLSToBGR_8u_P3R
ippiRGB565ToYUV422_16u8u_C3P3R
ippiRGBToCbYCr422Gamma_8u_C3C2R
ippiRGBToCbYCr422_8u_C3C2R
ippiRGBToYCbCr422_8u_C3C2R
ippiRGBToYCbCr422_8u_C3P3R
ippiRGBToYCbCr_8u_P3R
ippiRGBToYCrCb422_8u_P3C2R
ippiRGBToYUV420_8u_P3
ippiRGBToYUV420_8u_P3R
ippiRGBToYUV422_8u_C3C2R
ippiRGBToYUV422_8u_C3P3
ippiRGBToYUV422_8u_C3P3R
ippiRGBToYUV422_8u_P3
ippiRGBToYUV422_8u_P3R
ippiRGBToYUV_8u_AC4R
ippiRGBToYUV_8u_C3R
ippiRGBToYUV_8u_P3R
ippiYCbCr422To420_Interlace_8u_P3R
ippiYCbCr422ToBGR_8u_C2C3R
ippiYCbCr422ToBGR_8u_C2P3R
ippiYCbCrToRGB_8u_P3R
ippiYUV422ToRGB_8u_P3C3
ippiYUV422ToRGB_8u_P3C3R
ippiYUVToRGB_8u_P3C3R

ippiReconstructLumaIntra4x4_H264High_32s16u_IP1R
ippiFilterDeblockingLumaVerEdge_H264_16u_C1IR
ippiFilterDeblockingLumaHorEdge_H264_16u_C1IR

ippsFindCAny_8u
ippmInvert_m_32f
ippmMul_tm_32f

Functions not listed above are either hand-optimized for the Merom microarchitecture (SSSE3) or for prior SIMD instruction sets that are compatible with the Intel Atom processor (such as SSE2). In addition, the entire Intel Atom optimized library is compiler-optimized for the Intel Atom processor using the Intel Compiler xSSE3_ATOM switch (enable Atom optimizations) in order to take advantage of features unique to the Intel Atom processor.

Please see Optimized for the Intel® Atom™ Processor with Intel's Compiler for more information and check out the Intel Parallel Studio web site where you can learn more about the tools available to develop, debug, and tune your multi-threaded applications.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

The table below reflects the Intel AVX support provided in the Intel IPP 7.0.2 library release.

Intel AVX optimized code is available in both the 32-bit and 64-bit editions of the 7.0 library.

There is very limited support for Intel AVX in the 6.1 library; if you plan to use Intel IPP on an Intel AVX platform you should upgrade to the 7.0 version of the Intel IPP library.

Intel® AVX (Intel® Advanced Vector Extensions) is a 256-bit instruction set extension to SSE designed to provide even higher performance for applications that are floating-point intensive. Intel AVX adds new functionality to the the existing Intel SIMD instruction set (based on SSE) and includes a more compact SIMD encoding format. A large number (200+) of Intel SSEx instructions have been "upgraded" in AVX to take advantage of features like a distinct destination operand and flexible memory alignment. Approximately 100 of the legacy 128-bit Intel SSEx instructions have been promoted to process 256-bit vector data. In addition, approximately 100 new data processing and arithmetic operations, not present in the legacy Intel SSEx SIMD instruction set, have been added.

The primary benefits of Intel AVX are:

• Support for wider vector data (up to 256-bit).
• Efficient instruction encoding scheme that supports 3 and 4 operand instruction syntaxes.
• Flexible programming environment, ranging from branch handling to relaxed memory alignment requirements.
• New data manipulation and arithmetic compute primitives, including broadcast, permute, fused-multiply-add, etc.
  
  

ippGetCpuFeatures() reports information regarding the SIMD features available to your processor. Alternatively, ippGetCpuType() detects the processor type in your system. A return value of ippCpuAVX means your processor supports the Intel AVX instruction set. These functions are declared in ippcore.h.

Mask the value returned by ippGetCpuFeatures() with ippCPUID_AVX (0x0100) to determine if the Intel AVX SIMD instructions are supported by your processor (ippGetCpuFeatures() & ippCPUID_AVX is TRUE). To determine if your operating system also supports the Intel AVX instructions (saves the extended SIMD registers), mask the returned value from ippGetCpuFeatures() with ippAVX_ENABLEDBYOS (0x0200). Both conditions (i.e., CPU and OS support) must be met before your application can utilize the Intel AVX SIMD instructions.

The Intel IPP library has been optimized for a variety of SIMD instruction sets. Automatic "dispatching" detects the SIMD instruction set that is available on the running processor and selects the optimal SIMD instructions for that processor. Please review Understanding CPU Dispatching in the Intel® IPP Library for more information regarding dispatching.

Intel AVX optimization in the Intel IPP library consists of "hand-optimized" and "compiler-tuned" functions – code that has been directly optimized for the Intel AVX instruction set. Given the large number of primitives in the Intel IPP library, it is impossible to directly optimize every Intel IPP function for the large set of new instructions represented by the Intel AVX instruction set within the period of a single product release or update (processor-specific optimizations may also take into consideration cache size and number of cores/threads). Therefore, the functions in the table below represent those that either receive the greatest benefit from the new Intel AVX instructions or are the most widely used by Intel IPP customers.

If you have some specific Intel IPP functions that are not listed in the following table, and would like to see them added to the priority list for future AVX optimization, please create a thread on the IPP forum stating which functions you would like to see added to the AVX optimization priority list.

Functions directly optimized for Intel AVX are added to the table below as they become available with each new release or update of the library.

The following conventions are used in the table below to allow multiple similar functions to be denoted on a single line:

• {x} - Braces enclose a required (function name) element.
• [x] - Square brackets enclose an optional (function name) element.
• | - A vertical line indicates an exclusive choice within a set of optional or required elements.
• {x|y|z} - Example of three mutually exclusive choices within a required element in the function name.
• [x|y|z] - Example of three mutually exclusive choices within an optional element in the function name.

ippsAbs_{16s|32s|32f|64f}[_I] 
ippsAdd_{32f|32fc|64f|64fc}[_I] 
ippsAddC_{32f|64f}[_I] 
ippsAddProductC_32f 
ippsAddProduct_{32fc|64f|64fc} 
ippsAutoCorr_{32f|64f}
ippsConv_32f 
ippsConvert_{8s|8u|16s|16u|32s|64f}32f 
ippsConvert_{32s|32f}64f 
ippsConvert_32f{8s|8u|16s|16u}_Sfs 
ippsConvert_64f32s_Sfs 
ippsCopy_{16s|32s|32f|64f} 
ippsCrossCorr_{32f|64f} 
ippsDFTFwd_CToC_{32f|32fc|64f|64fc} 
ippsDFTFwd_RTo{CCS|Pack|Perm}_{32f|64f} 
ippsDFTInv_CCSToR_{32f|64f} 
ippsDFTInv_CToC_{32f|32fc|64f|64fc} 
ippsDFTInv_{Pack|Perm}ToR_{32f|64f} 
ippsDFTOutOrd{Fwd|Inv}_CToC_{32fc|64fc} 
ippsDiv[C]_32f[_I] 
ippsDotProd_32f64f 
ippsFFTFwd_CToC_{32f|32fc|64f|64fc}[_I] 
ippsFFTFwd_RTo{CCS|Pack|Perm}_{32f|64f}[_I] 
ippsFFTInv_CCSToR_{32f|64f}[_I] 
ippsFFTInv_CToC_{32f|32fc|64f|64fc}[_I] 
ippsFFTInv_{Pack|Perm}ToR_{32f|64f}[_I] 
ippsFIR64f_32f[_I] 
ippsFIR64fc_32fc[_I] 
ippsFIRLMS_32f 
ippsFIR_{32f|32fc|64f|64fc}[_I] 
ippsIIR32fc_16sc_[I]Sfs 
ippsIIR64fc_32fc[_I] 
ippsIIR_32f[_I] 
ippsLShiftC_16s_I 
ippsMagnitude_16sc_Sfs 
ipps{Min|Max}Indx_{32f|64f} 
ippsMul_32fc[_I] 
ippsMul[C]_{32f|32fc|64f|64fc}[_I] 
ippsMulC_64f64s_ISfs 
ipps{Not|Or}_8u 
ippsPhase_{16s|16sc|32sc}_Sfs 
ippsPowerSpectr_{32f|32fc} 
ippsRShiftC_16u_I 
ippsSet_{8u|16s|32s} 
ippsSqr_{8u|16s|16u|16sc}_[I]Sfs 
ippsSqr_{32f|32fc|64f|64fc}[_I] 
ippsSqrt_32f[_I] 
ippsSub_{32f|32fc|64f|64fc}[_I] 
ippsSubC_{32f|32fc|64f|64fc}[_I] 
ippsSubCRev_{32f|32fc|64f|64fc}[_I] 
ippsSum_{32f|64f} 
ippsThreshold_{32f|GT_32f|LT_32f}_[_I] 
ippsThreshold_{GT|LT}Abs_{32f|64f}[_I] 
ippsThreshold_GTVal_32f[_I] 
ippsWinBartlett_{32f|32fc|64f|64fc}[_I] 
ippsWinBlackman_{32f|64f|64fc}[_I] 
ippsWinBlackmanOpt_{32f|64f|64fc}[_I] 
ippsWinBlackmanStd_{32f|64f|64fc}[_I] 
ippsWinKaiser_{32f|64f|64fc}[_I] 
ippsZero_{8u|16s|32f}

ippgDFTFwd_CToC_8_64fc ippgDFTFwd_CToC_12_64fc 
ippgDFTFwd_CToC_16_{32fc|64fc}
ippgDFTFwd_CToC_20_64fc
ippgDFTFwd_CToC_24_64fc
ippgDFTFwd_CToC_28_64fc 
ippgDFTFwd_CToC_32_{32fc|64fc}
ippgDFTFwd_CToC_36_64fc
ippgDFTFwd_CToC_40_64fc
ippgDFTFwd_CToC_44_64fc 
ippgDFTFwd_CToC_48_{32fc|64fc}
ippgDFTFwd_CToC_52_64fc 
ippgDFTFwd_CToC_56_64fc 
ippgDFTFwd_CToC_60_64fc 
ippgDFTFwd_CToC_64_{32fc|64fc} 
ippgDFTInv_CToC_8_64fc 
ippgDFTInv_CToC_12_64fc 
ippgDFTInv_CToC_16_{32fc|64fc} 
ippgDFTInv_CToC_20_64fc 
ippgDFTInv_CToC_24_64fc 
ippgDFTInv_CToC_28_64fc 
ippgDFTInv_CToC_32_{32fc|64fc} 
ippgDFTInv_CToC_36_64fc 
ippgDFTInv_CToC_40_64fc 
ippgDFTInv_CToC_44_64fc 
ippgDFTInv_CToC_48_{32fc|64fc} 
ippgDFTInv_CToC_52_64fc 
ippgDFTInv_CToC_56_64fc 
ippgDFTInv_CToC_60_64fc 
ippgDFTInv_CToC_64_{32fc|64fc}

iippsDeinterleave_32f

ippsAdaptiveCodebookSearch_RTA_32f
ippsFixedCodebookSearch_RTA_32f
ippsFixedCodebookSearchRandom_RTA_32f
ippsHighPassFilter_RTA_32f
ippsLSPQuant_RTA_32f
ippsLSPToLPC_RTA_32f
ippsPostFilter_RTA_32f_I
ippsQMFDecode_RTA_32f
ippsSynthesisFilter_G729_32f

ippiRGBToHLS_8u_AC4R
ippiRGBToHLS_8u_C3R

ipprCastEye_32f
ipprCastShadowSO_32f
ipprDot_32f_P3C1M
ipprHitPoint3DEpsM0_32f_M
ipprHitPoint3DEpsS0_32f_M
ipprMul_32f_C1P3IM

ippiEigenValsVecs_[8u]32f_C1R 
ippiFilterGaussBorder_32f_C1R 
ippiMinEigenVal_[8u]32f_C1R 
ippiNorm_Inf_{8u|8s|16u|32f}_C{1|3C}MR 
ippiNorm_L1_{8u|8s|16u|32f}_C{1|3C}MR 
ippiNorm_L2_{8u|8s|16u|32f}_C{1|3C}MR 
ippiNormRel_L2_32f_C3CMR 
ippiUpdateMotionHistory_[8u|16u]32f_C1IR

ippiAddC_32f_C1[I]R 
ippiConvert_32f* 
ippiCopy_16s* 
ippiCopy_8u* 
ippiConvFull_32f_{AC4|C1|C3}R 
ippiConvValid_32f_{AC4|C1|C3}R 
ippiCrossCorrFull_NormLevel_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_64f_C1R 
ippiCrossCorrFull_NormLevel_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_NormLevel_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrFull_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrFull_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrSame_NormLevel_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_NormLevel_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrSame_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrSame_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrValid_{8u32f|8s32f|16u32f|32f}_C1R 
ippiCrossCorrValid_NormLevel_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_64f_C1R 
ippiCrossCorrValid_NormLevel_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_NormLevel_8u_{AC4|C1|C3|C4}RSfs 
ippiCrossCorrValid_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiCrossCorrValid_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiDCT8x8FwdLS_8u16s_C1R 
ippiDCT8x8Fwd_16s_C1[I|R] 
ippiDCT8x8Fwd_32f_C1[I] 
ippiDCT8x8Fwd_8u16s_C1R 
ippiDCT8x8InvLSClip_16s8u_C1R 
ippiDCT8x8Inv_16s8u_C1R 
ippiDCT8x8Inv_16s_C1[I|R] 
ippiDCT8x8Inv_2x2_16s_C1[I] 
ippiDCT8x8Inv_32f_C1[I] 
ippiDCT8x8Inv_4x4_16s_C1[I] 
ippiDCT8x8Inv_A10_16s_C1[I] 
ippiDCT8x8To2x2Inv_16s_C1[I] 
ippiDCT8x8To4x4Inv_16s_C1[I] 
ippiDFTFwd_CToC_32fc_C1[I]R 
ippiDFTFwd_RToPack_32f_{AC4|C1|C3|C4}[I]R 
ippiDFTFwd_RToPack_8u32s_{AC4|C1|C3|C4}RSfs 
ippiDFTInv_CToC_32fc_C1[I]R 
ippiDFTInv_PackToR_32f_{AC4|C1|C3|C4}[I]R 
ippiDFTInv_PackToR_32s8u_{AC4|C1|C3|C4}RSfs 
ippiDilate3x3_32f_C1[I]R 
ippiDilate3x3_64f_C1R 
ippiDivC_32f_C1[I]R 
ippiDiv_32f_{C1|C3}[I]R 
ippiDotProd_32f64f_{C1|C3}R 
ippiErode3x3_64f_C1R 
ippiFFTFwd_CToC_32fc_C1[I]R 
ippiFFTFwd_RToPack_32f_{AC4|C1|C3|C4}[I]R 
ippiFFTFwd_RToPack_8u32s_{AC4|C1|C3|C4}RSfs 
ippiFFTInv_CToC_32fc_C1[I]R 
ippiFFTInv_PackToR_32f_{AC4|C1|C3|C4}[I]R 
ippiFFTInv_PackToR_32s8u_{AC4|C1|C3|C4}RSfs 
ippiFilter_32f_{C1|C3|C4}R 
ippiFilter_32f_AC4R 
ippiFilter_64f_{C1|C3}R 
ippiFilter32f_{8s|8u|16s|16u|32s}_C{1|3|4}R 
ippiFilter32f_{8u|16s|16u}_AC4R 
ippiFilter32f_{8s|8u}16s_C{1|3|4}R 
ippiFilterBox_8u_{C1|C3}R 
ippiFilterBox_32f_{C1|C4|AC4}R 
ippiFilterColumn32f_{8u|16s|16u}_{C1|C3|C4|AC4}R 
ippiFilterColumn_32f_{C1|C3|C4|AC4}R 
ippiFilterGauss_32f_{C1|C3}R 
ippiFilterHipass_32f_{C1|C3|C4|AC4}R 
ippiFilterLaplace_32f_{C1|C3|C4|AC4}R 
ippiFilterLowpass_32f_{C1|C3|AC4}R 
ippiFilterMax_32f_{C1|C3|C4|AC4}R 
ippiFilterMedian_32f_C1R 
ippiFilterMin_32f_{C1|C3|C4|AC4}R 
ippiFilterRow_32f_{C1|C3|C4|AC4}R 
ippiFilterRow32f_{8u|16s|16u}_{C1|C3|C4|AC4}R 
ippiFilterSobelHoriz_32f_{C1|C3}R 
ippiFilterSobelVert_32f_{C1|C3}R 
ippiMean_32f_{C1|C3}R 
ippiMulC_32f_C1[I]R 
ippiMul_32f_{C1|C3|C4}[I]R 
ippiResizeSqrPixel_{32f|64f}_{C1|C3|C4|AC4}R 
ippiResizeSqrPixel_{32f|64f}_{P3|P4}R 
ippiSqrDistanceFull_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceFull_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiSqrDistanceSame_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceSame_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiSqrDistanceValid_Norm_16u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_8s32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_8u32f_{AC4|C1|C3|C4}R 
ippiSqrDistanceValid_Norm_8u_{AC4|C1|C3|C4}RSfs 
ippiSqrt_32f_C1R 
ippiSqrt_32f_C3IR 
ippiSubC_32f_C1[I]R 
ippiSub_32f_{C1|C3|C4}[I]R 
ippiSum_32f_C{1|3}R 
ippiTranspose_32f_C1R

ippiPCTFwd_JPEGXR_32f_C1IR 
ippiPCTFwd16x16_JPEGXR_32f_C1IR 
ippiPCTFwd8x16_JPEGXR_32f_C1IR 
ippiPCTFwd8x8_JPEGXR_32f_C1IR 
ippiPCTInv_JPEGXR_32f_C1IR_128 
ippiPCTInv16x16_JPEGXR_32f_C1IR 
ippiPCTInv8x16_JPEGXR_32f_C1IR 
ippiPCTInv8x8_JPEGXR_32f_C1IR

Those functions that have not been directly optimized for AVX (i.e., functions that do not appear in the table) have been compiled using the Intel Compiler "xG" switch (enable AVX optimization). Additional performance improvements are achieved by adherence to an AVX ABI (application binary interface) feature that inserts the special AVX "vzeroupper" instruction after any function with AVX code to eliminate any AVX to SSE transition penalties.

For those functions that are not directly optimized for AVX, the g9/e9 library utilizes optimizations from prior compatible SSE optimizations, such as those tuned for the p8/y8 libraries and preceding SIMD optimizations (e.g., SSE4.x, AES-NI and SSE2/3). Thus, functions not listed above will include the highest level of directly optimized code based on the AES-NI, SSE4.x, SSSE3, SSE3 and SSE2 SIMD instruction sets, wherever applicable.

For more information about the g9/e9 optimization layer and Intel AVX in the Intel IPP library, please refer to the Intel Integrated Performance Primitives for Windows* OS on Intel® 64 Architecture 'User's Guide'.

Review How to Compile for Intel® AVX for more information and check out the Intel Parallel Studio web site where you can learn more about the tools available to develop, debug, and tune your multi-threaded applications.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Intel^® Integrated Performance Primitives (Intel^® IPP) is an extensive library of multicore-ready, highly optimized software functions for digital media and data-processing applications. Intel^® IPP offers thousands of optimized functions covering frequently-used fundamental algorithms. Intel IPP functions are designed to deliver performance beyond what optimized compilers alone can deliver. More information about IPP can be retrieved at http://www.intel.com/software/products/ipp/index.htm.

OpenCV is an acronym for Open Source Computer Vision Library. The library is a well-known software library in computer vision for both academic and commercial use.  It is free, open source software and provides developers an easy way to input, display and store video and images, and also provides over 500 routines for computer vision processing, image processing, face detection and tracking, machine learning, etc. More information about OpenCV can be found at http://opencv.willowgarage.com/wiki/FullOpenCVWiki.

In early OpenCV versions, OpenCV was automatically accelerated by taking advantage of Intel® Integrated Performance Primitives (Intel® IPP). However, the latest OpenCV version 2.1.0 doesn't incorporate Intel® IPP by default, thus the performance benefit of Intel® IPP functions which are optimized via the Streaming SIMD Extensions (SSE, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, and Intel® AVX in latest) instructions, cannot be obtained automatically.

With the technical notes, we will show how to use Intel® IPP with latest OpenCV as well as how to integrate Intel® IPP into OpenCV.  Two test cases are provided to demonstrate the details.

• Use Intel® IPP library and OpenCV library independently
  Test case: transpose a image via cvRemap and ippiRemap
• Integrate Intel® IPP library into OpenCV library and use OpenCV with built-in Intel® IPP
  Test case: Measures image similarity via cvMatchTemplate() with default OpenCV library and OpenCV library with built-in-IPP
• Compare OpenCV, OpenCV with built-in Intel® IPP,  and Intel® IPP
  Perfromance test: cvMatchTemplate() in OpenCV and in OpenCV with built-in Intel® IPP,  ippiCrossCorrValid_Norm()
  
  Attached the documentation and test case.
  OpenCV_ApplicationNotes.pdf,
  ImageTranspose.cpp,
  correlation_ipp_opencv.cpp,
  Sample in Microsoft Visual Studio 2008 and Intel® VTune Amplifer XE 2011
  IPP_OpenCV2.1_Sample.zip (See attached zip file)
  

  
  Summary

  Intel® IPP is a software library provided by Intel® software group. It offers over 10K highly optimized fundamental functions for multimedia, data and image processing application. OpenCV is free and open for both non-commercial and commercial use. It provides cross-platform middle-to-high level functions for popular computer vision algorithms. OpenCV can be built with Intel® Integrated Performance Primitives (IPP). This makes it fast on all the architectures supported by the library, where the optimal code for each host architecture is chosen at runtime.

  In this paper, we showed how to integrate Intel® IPP into OpenCV step by step. With the two samples, we also discovered how OpenCV library with built-in Intel® IPP works, demonstrated how to use Intel® IPP with latest OpenCV library as well as how to use OpenCV with built-in Intel® IPP. In summary, the OpenCV library supports more computer vision algorithms than the Intel IPP library. Intel IPP library provides low-level but high performance basic image and video processing functions. We can use them as two independent libraries. However, it is convenient to integrate IPP and OpenCV via OpenCV build process and the Have_IPP flag. Thus we can benefit Intel IPP integrated into the OpenCV library automatically. In regard to the performance of routines with the same functionality in Intel® IPP and OpenCV, the direct IPP function call has the best performance. It is about 5x faster than the default OpenCV library and 2.21x the OpenCV library with built-in ipp under two cores @2.13G.  Taking considering of the fact of OpenCV itself can be built in parallel and OpenCV also includes SSE2-optimized code for many of functions, we recommend using OpenCV with calls to stand alone Intel® IPP, or OpenCV with built-in Intel IPP according to the application's feature and performance requirements.

   

  Refer to our Optimization Notice for more information regarding performance and optimization choices in Intel software products.

20 sep 2011 – article update – the ZIP file has been updated to include a missing DLL and it also now contains both AWK and GAWK executables. If you already have the necessary UNIX utilities on your Windows system (e.g., Cygwin or MinGW) you may not need the contents of the ZIP file. In any case please download the "ipp-fn-survey.awk" script file, it is required regardless of the UNIX utilities you use to run the script! On Windows, this AWK script has only been verified against the old GnuWin32 utils provided here. The GnuWin32 utils distributed in the attached ZIP file can be found here: http://gnuwin32.sourceforge.net/packages.html.

In the interest of developing a list of "most frequently used" functions by customers of the Intel IPP library, we have created a simple AWK script that can be used on either a Windows or Linux system to extract the names of the Intel IPP functions used in your application, without having to reveal any of your application source.

The number of Intel IPP functions present in the library is quite large; as a result, optimizing the entire library for new SIMD architectures must be performed in phases. In general, we would like to optimize first those functions that are most popular and relevant to our customers, in order to insure that your applications receive the maximum benefit as new SIMD architectures and/or extensions to those architectures are introduced.

Attached to this KB article are two files:

• ipp-fn-survey.awk
• GnuWin32-utils.zip

The AWK script scans C/C++ source code to identify any function that conforms to the standard naming scheme used by the Intel IPP library. This AWK script is provided in source format, so you can inspect the script to determine exactly what it does.

In essence, this script:

1. removes /* */ and // style comments to avoid false detects within comments
2. removes " " string constants to avoid false detects within strings
3. searches for and lists the names of all Intel IPP "core" functions
4. searches for and lists the names of all Intel IPP "administrative" functions

The script is not perfect and may miss a few Intel IPP functions. Please see the comments inside the AWK script for more details on known or suspected issues.

If the source tree you scan includes the IPP header files (ippac.h, ippcc.h, ippch.h, etc.) be sure to exclude those files from the search; otherwise, you will include every IPP function listed in those headers, even if you are not using them in your source code.

Basic Operation on Windows:

To run this script on a Windows machine you will need a copy of the GnuWin32 GAWK application (or a compatible AWK). In order to build a concise and sorted list of the Intel IPP functions used within your application it is also helpful to utilize the UNIX-compatible find, sort and uniq functions. All of these functions are provided in the GnuWin32-utils.zip attachment to this KB article. With the GnuWin32 applications installed on your Windows system, use the following command line:

>find src_dir -regex ".+\.[ch]p*" -exec gawk -f ipp-fn-survey.awk {} ; | sort | uniq >ipp-survey.txt

where "src_dir" is the root of the directory you wish to scan source for names of IPP functions -- simplest way to do this is to copy the AWK file and the contents of the ZIP file (GnuWin32-utils-zip) to "src_dir" and type:

>find . -regex ".+\.[ch]p*" -exec gawk -f ipp-fn-survey.awk {} ; | sort | uniq >ipp-survey.txt

Note: on a Windows system "find" needs to be a UNIX compatible version of find, not the Microsoft find. To avoid name conflicts with the Microsoft find.exe you might need to rename the GnuWin32 "find.exe" file to "uxfind.exe" and then run the samples above by referencing "uxfind" rather than "find" at the beginning of each script execution command.

If you used the command line above, the results of the scan will be found in the file named "ipp-survey.txt" in the starting directory.

Basic Operation on Linux:

To run this script on a Linux machine you will need the standard Gnu AWK, find, sort, uniq and xargs utilities that are normally present on your Linux system. Use the following command line:

$find src_dir -iregex ".+\.[ch]p*" | xargs ./ipp-fn-survey.awk | sort | uniq >ipp-survey.txt

where "src_dir" is the root of the directory you wish to scan source for names of IPP functions -- simplest way to do this is to copy this AWK file to the "src_dir" and type:

$find . -regextype posix-awk -iregex ".+\.[ch]p*" | xargs ./ipp-fn-survey.awk | sort | uniq >ipp-survey.txt

Note: GAWK on some Linux systems may not honor IGNORECASE -- resulting in a few false finds. Also, make sure the "executable" bits are set properly on the AWK script.

If you used the command line above, the results of the scan will be found in the file named "ipp-survey.txt" in the starting directory.

On some Linux systems you may not have gawk but awk installed on your system. The first line of the ipp-fun-survey.awk file references /usr/bin/gawk as the script interpreter. If your system instead only contains /usr/bin/awk you need to change that first line. To determine which application is on your system type "which gawk" at a command prompt. If nothing is returned type "which awk" at the command line. If your system only contains awk, or the application is located someplace other than /usr/bin, you will have to edit the first line of the ipp-fn-survey.awk script.

Terms and Conditions

This script will not reveal any source code or parameter names, only the names of the IPP functions referenced in the source code that it scans.

Note that this script is being provided under the terms and conditions of the Intel IPP EULA. Please insure you agree to those terms before using the script to provide us with a list of the Intel IPP primitives you are using.

If you are able to run this script (or something similar) on your application source code and generate a list of IPP functions that you would like to share with us, please reply to this posting (using the private option, if you prefer) with some information about your company and your application, as well as the list of Intel IPP functions created by the script or an email address you may use to contact you directly. Your input is very valuable for the prioritization of future optimizations within the Intel IPP library.

IMPORTANT! The minimum SIMD instruction levels supported by version 7.0 of the Intel IPP library has changed! Applications built with this version of the library require that processors must support at least the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instruction set when built for Intel IA-32 processors (ia32) and the Intel® Streaming SIMD Extensions 3 (Intel® SSE3) instruction set when built for Intel® 64 processors (intel64). The non-optimized layers of the library (px on ia32 and mx on intel64) have been removed; the w7 and m7 optimization layers are now the default optimization layers.

The standard distribution of the Intel IPP library contains multiple, functionally-identical, SIMD-specific, optimized libraries (or layers) that are automatically “dispatched” at run-time. The “dispatcher” directs your calls to the appropriate optimized library layer based on SIMD capabilities discovered during library initialization. This is done to maximize each function’s use of the runtime processor's underlying SIMD instructions and other architecture-specific features.

Note: you can build custom processor-specific libraries that do not require the dispatcher, but that is outside the scope of this article. Please read this IPP linkage models article for information on how to build custom versions of the IPP library.

Dispatching selects the Intel IPP optimized library layer that corresponds to the runtime CPU's SIMD instruction set. For example, on a Windows installation, the $(IPPROOT)\..\redist\intel64\ipp directory contains a file named ippiu8-7.0.dll which contains version ‘7.0’ of the optimized image processing libraries for processors that support the Intel SSE3 instructions on 64-bit processors; ‘ippi’ denotes the image processing domain, ‘u8’ denotes the SSSE3 instructions set for 64-bit processors and ‘7.0’ denotes the library’s version number.

In the general case, the “dispatcher” identifies the run-time processor only once, at library initialization time, and sets up a variable internal to the library that directs your calls to the SIMD-specific functions that match the runtime processor. For example, ippsCopy_8u(), has multiple implementations stored in the library, with each version optimized to a specific SIMD instruction set. The u8_ippsCopy_8u() version of ippsCopy_8u() is called by the dispatcher when running on an Intel® Core 2 Duo® processor in 64-bit addressing mode, because u8_ippsCopy_8u() is optimized for the SSSE3 instruction set architecture supported by that processor in 64-bit addressing mode.

Note: IPP architectures generally correspond to SIMD (MMX, SSE, AES, etc.) instructions sets, with some minor variations (see the p8 and y8 optimization layers).

Initializing the IPP Dispatcher

Identifying the runtime processor and initializing the dispatcher should be the first action you take with the Intel IPP library. If you are using the standard dynamic link library this process is handled automatically when the Intel IPP shared library is initialized. If you are using a static library you must perform this step manually. See this article on the ipp*Init*() functions for more information on how to do this.

Because the minimum SIMD instruction set is SSE2 on IA-32 and SSE3 on Intel 64 processors it is recommended that you ALWAYS call the the ippInit() function before making any other calls to the Intel IPP library. This advice applies regardless of whether you are linking against the static or dynamic form of the library (even though the dynamic library will also perform this call).

Calling the ippInit() function with the shared libraries (DLL and SO) will generate an error message to a dialog box or error console if the ippInit() function detects that the runtime CPU is not supported by the Intel IPP library. Calling the ippInit() function in the static versions of the library will not generate a console or dialog message. Both versions of the ippInit() function will return an error code when a non-supported CPU is detected.

It is important that you call the ippInit() function at the beginning of your application to insure that the processor on which your application is running will support the Intel IPP library. If the ippInit() function returns an error code you should close your application gracefully in order to avoid an unexpected termination of your application by an invalid instruction fault because your application is running on an unsupported processor.

The following table lists the SIMD architecture codes supported by version 7.0 of the Intel IPP library.

For non-Intel based processors support, please read Use Intel® IPP on Intel or Compatible AMD* Processors.

If you compare this dispatch table above to the 5.3 thru 6.1 dispatch table you will note that the Intel SSE3 optimization layer (t7) has been removed from the 32-bit edition (ia32) of the library. 32-bit applications built with the 7.0 version of the library that execute on an SSE3 processor will automatically use the Intel SSE2 optimization layer (w7). In most cases, the impact of this change is minor, since the performance difference between the Intel SSE3 (t7) and Intel SSE2 (w7) optimization layers in the Intel IPP library is minimal. Processors that support the Intel SSSE3 instruction set (v8 and s8 optimization layers) are not affected by this change. (Note: this change does not impact applications built using the 64-bit edition of the library, which now uses the Intel SSE3 optimization layer (m7) as its default path.)

P8/Y8 Internal Run-Time Dispatcher

Within the 32-bit p8 and equivalent 64-bit y8 architectures there is an additional "runtime dispatcher," a mini-dispatcher. The Nehalem and Westmere processor microarchitectures add additional SIMD instructions beyond those defined by SSE4.1. The Nehalem processor microarchitecture added SSE4.2 SIMD instructions and the Westmere processor microarchitecture added Inte® AES-NI.

Creating two separate optimization layers within the IPP library for the small set of instructions added by SSE4.2 and AES-NI would be very space inefficient, so they are bundled into the SSE4.1 library (p8/y8) as minor variants to that optimization layer. When you call a function that includes, for example, AES-NI optimizations, an additional jump directs your call to the AES-NI version within the p8/y8 library if your runtime processor supports these instructions. Because the enhancements affect the optimization of only a small number of Intel IPP functions, this additional overhead occurs infrequently and only when your application is executing on a p8/y8 architecture processor that supports these extra instructions.

S8/N8 (Atom) Dispatch

Unlike preceding versions of the library, the 7.0 version of the Intel IPP library does include Atom-optimized variants of the library within all formats (static and dynamic) of the library. For this reason, the Linux distribution of the 7.0 version of the Intel IPP library no longer includes a separate Atom-specific version of the library, since Atom-specific optimizations have been fully merged into all formats of the standard library files.

Please read Intel® Atom™ Processors Support in the Intel® Integrated Performance Primitives (Intel® IPP) Library for more information regarding Atom optimizations in the IPP library.

Processor Architecture Table

The following table was copied from an Intel Compiler Pro options article describing some compiler architecture options. It contains a list of Intel processors showing which processors support which SIMD instructions. For the latest table please refer to the original article; it gets updated on a regular basis. Please note that the behavior of the Intel Compiler SIMD dispatcher described in that article does not apply to the Intel IPP library.

The Intel IPP library dispatching mechanism behaves differently than that found in the Intel Compiler products, and may also behave differently than other Intel library products.

Additional information regarding dispatching and how it relates to non-Intel processors can be found here. How to identify your specific processor is described here. To correlate a processor family name with an Intel CPU brand name, use the following web site: ark.intel.com.

SSE4.2
Intel® Core™ i7 processors
Intel® Core™ i5 processors
Intel® Core™ i3 processors
Intel® Xeon® 55XX series

SSE4.1
Intel® Xeon® 74XX series
Quad-Core Intel® Xeon 54XX, 33XX series
Dual-Core Intel® Xeon 52XX, 31XX series
Intel® Core™ 2 Extreme 9XXX series
Intel® Core™ 2 Quad 9XXX series
Intel® Core™ 2 Duo 8XXX series
Intel® Core™ 2 Duo E7200

SSSE3
Quad-Core Intel® Xeon® 73XX, 53XX, 32XX series
Dual-Core Intel® Xeon® 72XX, 53XX, 51XX, 30XX series
In tel® Core™ 2 Extreme 7XXX, 6XXX series
Intel® Core™ 2 Quad 6XXX series
Intel® Core™ 2 Duo 7XXX (except E7200), 6XXX, 5XXX, 4XXX series
Intel® Core™ 2 Solo 2XXX series
Intel® Pentium® dual-core processor E2XXX, T23XX series

SSE3
Dual-Core Intel® Xeon® 70XX, 71XX, 50XX Series
Dual-Core Intel® Xeon® processor (ULV and LV) 1.66, 2.0, 2.16
Dual-Core Intel® Xeon® 2.8
Intel® Xeon® processors with SSE3 instruction set support
Intel® Core™ Duo
Intel® Core™ Solo
Intel® Pentium® dual-core processor T21XX, T20XX series
Intel® Pentium® processor Extreme Edition
Intel® Pentium® D
Intel® Pentium® 4 processors with SSE3 instruction set support

SSE2
Intel® Xeon® processors
Intel® Pentium® 4 processors
Intel® Pentium® M

IA32
Intel® Pentium® III Processor
Intel® Pentium® II Processor
Intel® Pentium® Processor

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

1. Build system requirement

Software:
•   Intel Parallel Studio 2011 and Microsoft* Visual Studio 2005 and later
•   (optional)  install static ipp library separately from http://software.intel.com/en-us/articles/intel-ipp-static-libraries/

Hardware:  The latest dual-core/Quad Core machine with Windows xp/Windows Vista/Windows 7

2. Download and Unzip the Resize_Image_PS_VS2005.zip to a directory, let's name <WorkDIR>

3. Go to <WorkDIR> and double click the Resize Image.sln.  The msvc2005 IDE will prompt automatically.

4. From the main toolbar select Project>> Intel Parallel Composer 2011 » Select Build Component.

(or right-click the Project in Solution Explorer) , check Use IPP. click OK

5. Then build the application, from the main toolbar select Build >> Build solution

Please see the build details in  Use Intel IPP in Intel® Parallel Composer

How to run the application 

1. Run the application
From the main toolbar, select Debug >> Start Without Debugging. The application windows start, Click Open File, Select LennaC1.bmp 

2. click menu "Process => Resize image" to Resize the image. 
 Enter the zoom factor in horizontal (x) and vertical (y) directory in Resize dialog box.  Click OK  

3: Click lennC1.bmp and repeat step 2 again, make sure click button USE_IPP. Then get the below image  

IPP Function Adoption: 
Assume the sample is the application we want to improve the performance via IPP function.  
1.  Find the c code resize image function in RESIZE.cpp

unsigned long C_Code_Resize(unsigned char * src, int srcWidth, int srcHeight,   int srcStep, unsigned char* dst, int dstWidth, int dstHeight, int dstStep, double m_zoom_x, double m_zoom_y, int interpolation)

 It is called by function ProcessImage(CSampleDoc *pSrc) in ippiAddC.cpp

2. Check ipp manual ippiman.pdf and find the function ippiResizeSqrPixel have same functionality.  Then replace the C function with IPP function.  
Declare a similiar function in RESIZE.cpp
unsigned long IPP_Resize( void* src, int srcWidth, int srcHeight,int srcStep,  void* dst,  int dstWidth, int dstHeight, int dstStep, double m_nzoom_x, double m_nzoom_y, int interpolation)

 And call it in ProcessImage(CSampleDoc *pSrc) in ippiAddC.cpp instead of call C_Code_Resize().  (In order to compare the performance, we keep the c function call here.)

 if (m_USE_IPP)
{
             ippStaticInit();
       //---- perform IPP Funtion Code to rotate a image  -----//
         run_time = IPP_Resize(pSrc->DataPtr(),pSrc->Width(),pSrc->Height(),pSrc->Step(),(Ipp8u*)pDst->DataPtr(),        pDst->Width(),pDst->Height(),pDst->Step(),m_zoom_x,m_zoom_y,m_Interpolation);
}
else{         //---- perform C Code to rotate a image  -----//
         run_time = C_Code_Resize((unsigned char *)pSrc->DataPtr(),pSrc->Width(),
         pSrc->Height(),pSrc->Step(), (unsigned char *)pDst->DataPtr(), pDst->Width(),pDst->Height(),pDst->Step(),m_zoom_x,m_zoom_y,m_Interpolation);
}     

3. Write the IPP code to replace the C code.  The table show the original C code and the IPP code 

Tthe C code

The IPP code

unsigned long C_Code_Resize(unsigned char * src, int srcWidth, int srcHeight,int srcStep, unsigned char* dst, int dstWidth, int dstHeight, int dstStep, double m_zoom_x, double m_zoom_y, int interpolation) {//---------- Perform 1 order linear ---      //define record time variable      unsigned long start_clock,stop_clock;    start_clock = RUNTIME;      const unsigned char *tmpSrc;     unsigned char *tmpRef;     int width = srcWidth;     int height = srcHeight;     double xInv = 1.0 /  m_zoom_x;     double yInv = 1.0 /  m_zoom_y;     int colInd, rowInd;     int i, j, xSrc0, xSrc1, ySrc0, ySrc1, wdroi, hdroi;     int idxl, idyt, icol, jrow;     double row, col;     double y1, y2, y3, y4, v, v1, v2, tempV,tempV2;      idxl=0;      idyt=0;      wdroi = dstWidth;     hdroi = dstHeight;      tmpSrc = src; for(int kloop=0;kloop<LOOP;kloop++)  {     tmpRef = dst ;     for (j = 0, jrow = idyt; j < hdroi; j++, jrow++) {         row = (jrow + 0.5) * yInv - 0.5;         rowInd = (int)floor(row);         ySrc0 = ts_iGetCoord_vs(rowInd, rowInd,  0, srcHeight, srcHeight);         ySrc1 = ts_iGetCoord_vs(rowInd, rowInd + 1, 0, srcHeight, srcHeight);         for (i = 0, icol = idxl; i < wdroi; i++, icol++) {              col = (icol + 0.5) * xInv - 0.5;             colInd = (int)floor(col);             xSrc0 = ts_iGetCoord_vs(colInd, colInd,   0, srcWidth, srcWidth);             xSrc1 = ts_iGetCoord_vs(colInd, colInd + 1, 0, srcWidth, srcWidth);             y1 = (double)tmpSrc[ySrc0 * srcStep + xSrc0];             y2 = (double)tmpSrc[ySrc0 * srcStep + xSrc1];             y3 = (double)tmpSrc[ySrc1 * srcStep + xSrc0];             y4 = (double)tmpSrc[ySrc1 * srcStep + xSrc1];    ts_iLinearCalcSP_vs(col + 0.5, colInd + 0.5, colInd + 1.5, y1, y2, &v1);            ts_iLinearCalcSP_vs(col + 0.5, colInd + 0.5, colInd + 1.5, y3, y4, &v2); ts_iLinearCalcSP_vs(row + 0.5, rowInd + 0.5, rowInd + 1.5, v1, v2, &v);               //(ts_isaturate_vs(v);             tempV = (int)(v + EXP + 0.5);             tmpRef[i] =(unsigned char)((tempV > 255) ? 255 : (tempV < 0) ? 0 : tempV);         }         tmpRef += dstStep;   }   }      stop_clock = RUNTIME;      int mhz;     ippGetCpuFreqMhz(&mhz);      return (stop_clock - start_clock)/mhz/LOOP; }

unsigned long IPP_Resize(void* src, int srcWidth, int srcHeight,int srcStep,  void* dst,  int dstWidth, int dstHeight, int dstStep,   double m_nzoom_x, double m_nzoom_y, int interpolation)   {       //   define record time variable     unsigned long start_clock,stop_clock;     start_clock= RUNTIME;  // define IPP function parameter      IppiRect srcRoi = {0,0, srcWidth, srcHeight};      IppiRect dstRoi={0,0, dstWidth,dstHeight};        IppiSize srcSize = {srcWidth, srcHeight};     IppiSize dstSize = {dstWidth, dstHeight};        int BufferSize;      ippiResizeGetBufSize(srcRoi, dstRoi, 1, interpolation, &BufferSize);      Ipp8u* pBuffer=ippsMalloc_8u(BufferSize);        for(int i=0;i<LOOP;i++)          //---------- Perform IPP function:ippiResizeSqrPixel_8u_C1R  -------------------------------------------//      ippiResizeSqrPixel_8u_C1R((Ipp8u*)src, srcSize, srcStep, srcRoi, (Ipp8u*)dst, dstStep, dstRoi, m_nzoom_x,m_nzoom_y,0, 0, interpolation, pBuffer);     ippsFree(pBuffer);     stop_clock = RUNTIME;       int mhz;     ippGetCpuFreqMhz(&mhz);      return (stop_clock - start_clock)/mhz/LOOP;

Performance Gain 

On one test machine (core 2 Quad 2.66GHz), as the result image show that the performance gain is 15654/353=44x.

The test is linking serial IPP static library.  As the ippiResize is threaded in dynamic library and threaded IPP static library. If enable the multithread, the performance gain will be more than 50x (depends on the core numbers and image size).

Conclusion
Intel® Parallel Studio 2011 provide developer a first suit of tool for easy developing parallel application on multi-core platform. IPP is part of key component of Intel® Parallel Studio. It provide over thousands highly-optimizated functions that offer the support for for developing high performance digital media application. This article describes a brief way to adopt IPP function instead of source code via Parallel Studio Project and gain over 40x performance speed up outright.  

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

The names in the table above are for the Windows version of the library. Linux library filenames are similar but begin with the prefix "lib" and end with a ".a" suffix if they are static link libraries and ".so" if they are shared libraries (dynamic link).

The 7.0 static libraries that end in an "_l" are single-threaded libraries; those that end in an "_t" are multi-threaded libraries. The 7.0 dynamic link libraries are only available in a multi-threaded format. There is no difference in naming between 64-bit and 32-bit in the 7.0 library.

The 6.1 library 64-bit names include an "em64t" suffix, this is not the case for the 7.0 library. The 6.1 threaded static library names end with an "_t" suffix; unlike the 7.0 library, the 6.1 single-threaded static libraries do not include a special suffix. In the 6.1 static library there is a third library component file that is common to both single-threaded and multi-threaded variants of the static library: the "ipp[*]emerged" file; this file is not listed in the table above, but must be included as part of the link line when linking either form of the 6.1 static library. The 6.1 dynamic link libraries are only available in a multi-threaded format.

Use the static libraries to build a custom dynamic link library.

Domain	Header File	Dynamic Linking	Static Linking
Audio Coding	ippac.h	ippac.lib	ippac_l.lib ippac_t.lib
Color Conversion	ippcc.h	ippcc.lib	ippcc_l.lib ippcc_t.lib
String Operation	ippch.h	ippch.lib	ippch_l.lib ippch_t.lib
Cryptography	ippcp.h	ippcp.lib	ippcp_l.lib ippcp_t.lib
Computer Vision	ippcv.h	ippcv.lib	ippcv_l.lib ippcv_t.lib
Data Compression	ippdc.h	ippdc.lib	ippdc_l.lib ippdc_t.lib
Data Integrity	ippdi.h	ippdi.lib	ippdi_l.lib ippdic_t.lib
Image Processing	ippi.h	ippi.lib	ippac_l.lib ippac_t.lib
Image Compression	ippj.h	ippj.lib	ippj_l.lib ippj_t.lib
Realistic Rendering and 3D Data Processing	ippr.h	ippr.lib	ippr_l.lib ippr_t.lib
Small Matrix Operations	ippm.h	ippam.lib	ippm_l.lib ippm_t.lib
Signal Processing	ipps.h	ippas.lib	ipps_l.lib  ipps_t.lib
Speech Coding	ippsc.h	ippsc.lib	ippsc_l.lib ippsc_t.lib
Video Coding	ippvc.h	ippvc.lib	ippvc_l.lib ippvc_t.lib
Vector Math	ippvm.h	ippvm.lib	ippvm_l.lib ippvm_t.lib
Generated Functions	ippgen.h	ippgen.lib	ippgen_l.lib ippgen_t.lib
Core Functions	ippcore.h	ippcore.lib	ippcore_l.lib ippcore_t.lib

The names in the table above are for the Windows version of the library. Linux library filenames are similar but begin with the prefix "lib" and end with a ".a" suffix if they are static link libraries and ".so" if they are shared libraries (dynamic link).

Static libraries that end in an "_l" are single-threaded libraries. Those that end in an "_t" are multi-threaded libraries. The dynamic link libraries are only available in a multi-threaded format.

Use the static libraries to build a custom dynamic link library.

To download and get more information about the IPP 7.0 Beta visit the IPP 7.0 beta program home page.

• Intel® IPP Main Product Page
• Intel® IPP 7.0 Library Release Notes
• Intel® IPP 7.0 Library Installation Guide
• Intel® IPP 7.0 Library System Requirements
• Intel® IPP 7.0 Library Getting Started
• Intel® IPP 7.0 Library Bug Fixes

Links to documentation, help, and code samples can be found on the main Intel IPP product page. For technical support visit the Intel IPP technical support forum and review the articles in the Intel IPP knowledgebase.

Please register your product using your preferred email address. This helps Intel recognize you as a valued customer in the support forum and insures that you will be notified of product updates. You can read Intel's Online Privacy Notice Summary if you have any questions regarding the use of your email address for software product registration.

How to Build an IPP Application provides an introduction to compiling, linking and deploying Intel IPP applications.

Intel IPP and Intel Parallel Studio and/or Intel Composer

The instructions in this article are intended for users of the stand-alone version of the Intel IPP library, or for those developers who wish to use their own makefiles or need to customize their Visual Studio solution files for building Intel IPP applications.

If your Intel IPP library was installed as a component of an Intel "suite product" (such as Intel Parallel Studio and Intel Composer) that has been "integrated" into Visual Studio, you may be able to ignore the environment configuration instructions on this page. Instead, please use the configuration tools that were added into Visual Studio for enabling the use of the Intel IPP library within that environment.

Regardless, the following information may be useful to review as it will help you understand how the library is organized on your development system and may provide hints regarding the best way to configure your development system for building an Intel IPP application.

Environment Variables

A script (batch file on Windows, shell script on other platforms) located in the ...\ipp\bin directory can be used to set the IPPROOT, LIB, INCLUDE and any required system-specific environment variables to point to the appropriate IPP library directories. Use of this script is an optional, but convenient, means by which to configure your development system for compiling and linking with the IPP library.

You run the script with a single input that specifies the primary processor architecture of interest. For example, ippvars.bat ia32 configures the environment variables for compiling and linking a 32-bit IPP application. Likewise, ippvars.bat intel64 configures your development environment to build 64-bit IPP applications.

Note: in the text that follows, <arch> refers to the primary processor architecture: ia32 or intel64, and <IPPROOT> refers to the IPP installation directory. Additionally, '\' and '/' are used interchangeably as directory separators.

An alternate architecture-specific script file is located in the <IPPROOT>\bin\<arch> directory that can be run without any input parameters. It calls the ippvars script mentioned above with the appropriate architecture as an input parameter.

Once defined, you can reference the IPPROOT variable within your makefiles and/or project files to locate the header and library files necessary to compile and link applications using the Intel IPP library.

Before running the build scripts provided with the IPP sample applications you must first be sure to set the IPPROOT environment variable to point to the IPP installation directory on your system. IPPROOT must point to that directory which contains the IPP bin, lib, include and tools directories. The sample build scripts will reference the IPPROOT environment variable in order to locate the IPP library and any additional tools required.

On a Windows system the following batch files are available to configure the environment for building IPP applications:

<IPPROOT>\bin\ippvars.bat  <arch>

or

IA-32 Intel® Architecture:  <IPPROOT>\bin\ia32\ippvars_ia32.bat
Intel® 64 Architecture:  <IPPROOT>\bin\intel64\ippvars_intel64.bat

On a Linux system the following shell scripts are available to configure the environment for building IPP applications:

<IPPROOT>/bin/ippvars.sh  <arch>

or

IA-32 Intel® Architecture:  <IPPROOT>/bin/ia32/ippvars32.sh
Intel® 64 Architecture:  <IPPROOT>/bin/intel64/ippvarsintel64.sh
Intel® Atom™ Processor:  <IPPROOT>/bin/lp32/ippvars32.sh

Include Files

The Intel IPP functions and structures are defined within several header files in the <IPPROOT>\include directory. The "ipp.h" header file includes all of these. For forward compatibility it is best to include only the ipp.h header file.

Calling Intel IPP Functions

The dynamic library dispatcher and merged static library mechanisms (described below) are designed to make the process of calling an Intel IPP functions as simple as calling any C function. Multiple SIMD-optimized versions of each function are concealed behind a single entry point.

See the following knowledgebase articles for more information on linking with the Intel IPP library:

Intel® IPP Linkage Models - Quick Reference Guide
Simplified Link Instructions for the IPP Library

And review these articles for information regarding the IPP dispatching mechanism:

Understanding CPU Dispatching in the Intel® IPP Library
IPP Dispatcher Control Functions - ipp*Init*() Functions

Using the Intel IPP Dynamic (Shared) Libraries

The Intel IPP library includes "stub" static library files that link to the correct entry points and automatically load the appropriate Intel IPP dynamic (shared) libraries at run time. To use the IPP dynamic libraries you must link with the library files located in the <IPPROOT>\lib\<arch>\ directory.

At run time the dynamic libraries will automatically detect the CPU type and load the correct processor-specific library files. The processor-specific dynamic libraries include tags like w7, v8 and p8 within their names. The only requirements necessary to use the dynamic libraries, once you have linked against the corresponding "stub" static libraries, is to insure that the shared libraries are located in the system path.

Note: the environment scripts described above, in the Environment Variables section, will correctly locate your dynamic library files in the appropriate system path.

On a Linux system be sure the Intel IPP shared libraries are part of the system variable LD_LIBRARY_PATH. For example, if the shared libraries are located in the <IPPROOT>/../redist/ia32/ipp folder, then the following command line should be entered:

export LD_LIBRARY_PATH=$IPPROOT/../redist/ia32/ipp/sharedlib:$LD_LIBRARY_PATH

Multi-threading (Multi-Core) Support

Intel IPP 7.0 uses the Intel OpenMP library to implement multi-threading within the library to support multiple hardware threads or cores. In some cases you can use OpenMP environment variables and APIs to control the OpenMP threading behavior within the IPP library. For detailed information regarding OpenMP and the Intel IPP library, please refer to the IPP reference manuals and the following knowledgebase articles:

Intel® IPP - Threading / OpenMP* FAQ
OpenMP and the Intel® IPP Library

Note: You must include the appropriate OpenMP shared-library file in your PATH. There are known incompatibilities between various versions of the OpenMP libraries. If you encounter problems, make sure that there is only one version of OpenMP located in your PATH environment variable.

Please read the following knowledgebase articles for information regarding the IPP library processor codes:

Understanding CPU Dispatching in the Intel® IPP Library
IPP Dispatcher Control Functions - ipp*Init*() Functions

Building a Custom Dynamic (Shared) Library

Please see the following knowledgebase article and the IPP documentation for information on building a custom dynamic library:

Intel® IPP Linkage Models - Quick Reference Guide

Using the Intel IPP Performance Benchmark Tool

The Intel IPP library includes a tool named "perfsys" to evaluate the performance of each Intel IPP function.
For more details on running perfsys please review the readme.htm file located in the <IPPROOT>\tools\<arch>\perfsys directory.