IPP Texture Compression Functions

Last Modified On :   June 23, 2009 12:18 AM PDT
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IPP Texture Compression Functions

Intel® IPP implements the Microsoft DirectX* texture compression algorithms (DXTC or DXTn) also known as S3 Texture Compression [S3TC]. It is a lossy compression with a fixed compression ratio of 4:1 or 8:1. This compression is a form of block truncating coding (BTC), where an image is divided into non-overlapping blocks and pixels in each block are quantized to a limited number of values.
Intel® IPP supports three variations of the S3TC algorithm: DXT1, DXT3, and DXT5.

Texture format - DXT1
• Compress 4x4 pixel block at time
• Format reduces the memory required from 48 bytes (16 colors x 3 components/color x byte/component) to 8 bytes of memory.
• Instead of storing 16 colors, the algorithm saves 2 reference colors and 16 2-bit color indexes.

Texture format - DXT3
• Compress 4x4 pixel block at time
• Format reduces the memory required from 64 bytes (16 colors x 4 components/color x 1 byte/component) to
  16 bytes of memory.
• Store colors as DXT1.
• Store Alpha as 16 separate 4 bit values

Texture format - DXT5
• Compress 4x4 pixel block at time
• Format reduces the memory required from 64 bytes (16 colors x 4 components/color x 1 byte/component) to 16
   bytes of memory.
• Store colors as DXT1.
• Store Alpha similarly as DXT1 store color data (the algorithm stores 2 reference alphas and 16 3-bit color indexes

List of Texture Compression functions in Intel IPP (IPP 6.1 Onward)

ippiTextureEncodeBlockFromRGBA_DXT1_8u_C4C1R
ippiTextureDecodeBlockToRGBA_DXT1_8u_C1C4R
ippiTextureEncodeBlockFromRGBA_DXT3_8u_C4C1R
ippiTextureDecodeBlockToRGBA_DXT3_8u_C1C4R
ippiTextureEncodeBlockFromRGBA_DXT5_8u_C4C1R
ippiTextureDecodeBlockToRGBA_DXT5_8u_C1C4R
ippiTextureEncodeBlockFromYCoCg_DXT5_8u_C3C1R

Additional Information about Texture Compression

IPP Texture Compression function description- IPP Documentation - Volume 2: Image and Video Processing [PDF 9.3MB]
J.M.P. van Waveren "Real-Time DXT Compression", http://cache-www.intel.com/cd/00/00/32/43/324337_324337.pdf





This article applies to: Intel® Integrated Performance Primitives Knowledge Base