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      <title>By Many-core task parallelism: low overhead task switching &amp;laquo; Defective Compass</title>
      <description><![CDATA[ n/a ]]></description>
      <link>http://software.intel.com/en-us/articles/itaniumr-processor-family-performance-advantages-register-stack-architecture/#comment-23622</link>
      <pubDate>Sun, 03 May 2009 23:47:02 -0700</pubDate>
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      <title>By Many-core task parallelism: low overhead task switching &amp;laquo; Defective Compass</title>
      <description><![CDATA[ n/a ]]></description>
      <link>http://software.intel.com/en-us/articles/itaniumr-processor-family-performance-advantages-register-stack-architecture/#comment-23653</link>
      <pubDate>Mon, 04 May 2009 16:36:16 -0700</pubDate>
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      <title>By Many-core task parallelism: low overhead task switching &amp;laquo; Defective Compass</title>
      <description><![CDATA[ n/a ]]></description>
      <link>http://software.intel.com/en-us/articles/itaniumr-processor-family-performance-advantages-register-stack-architecture/#comment-23727</link>
      <pubDate>Tue, 05 May 2009 14:20:45 -0700</pubDate>
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      <title>By Vishal K</title>
      <description><![CDATA[ Hi,

Lucid explanation. I'd like to know more about RSE spill mechanism and bursting out data to main memory. Thanks for the article. ]]></description>
      <link>http://software.intel.com/en-us/articles/itaniumr-processor-family-performance-advantages-register-stack-architecture/#comment-33108</link>
      <pubDate>Thu, 22 Oct 2009 05:48:37 -0700</pubDate>
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