Multi-Core Courseware Content from Intel

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Last Modified On :   October 28, 2008 7:09 AM PDT
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The course materials included in the Intel® Multi-Core Curriculum Initiative have been designed by experts on Intel software tools, technologies and initiatives and include lecture presentations, hands-on lab sessions and reference materials. More >>

Courseware Title Overview

For courseware details and download links please select from the titles below

1.a.1 Software Transactional Memory

1.a.2 Performance Library: Using Intel® Integrated Performance Primitives for Threading Applications (IPP)

1.a.3 Examples of Concurrent Solution Design

1.b.1 Multi-core Architecture & Fundamentals Tools (Compiler & VTune)

1.b.2 Parallel Programming Design Patterns

1.b.3 Threading Building Blocks and Libraries: Intel TBB

2.a Performance Library: Intel® Math Kernel Library (MKL)

3.a Threading Games for Performance

3.b Introduction to Parallel Programming

3.c Developing Applications for Intel® Multi-Core processors (Microsoft* .NET* Environment)

3.d Parallel Architecture for Games

4.a Multi-core Programming for Academia

 

Courseware Detail Section

1.a.1 Software Transactional Memory by S. Y. , July 2008, (link to overview page with further information and links)

Course / Module Description:
This module is a one hour brief introduction to Transactional Memory (TM) technology. The target audience should have experience in parallel/concurrent programming. They will learn about other synchronization alternatives and the lock mechanism.
In this module, rationale of TM will first be introduced, followed by an explanation of key concept of operating principles. The discussion focus will be on Software TM, the software implementation of TM, in which software support (compiler and libraries) and language extensions (key words) are illustrated with code examples.
On the completion of this module, audience will understand why and how Transactional Memory works for concurrent programming with the basic knowledge of the language extension for Software Transactional Memory (STM). This will allow them to be able to try STM and decide on whether or not to use it for their applications.

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1.a.2 Performance Library: Using Intel® Integrated Performance Primitives for Threading Applications by S.Y. , July 2008, (link to overview page with further information and links)

Course / Module Description:
The module introduces the Intel Performance Primitives (IPP) with regards to the library being used within multithreaded application development. It targets software developers who would like to have quick performance gains on threaded applications performance. This module introduces the basic architecture (or called API domains) of IPP, and focuses on how IPP helps threaded applications, which is achieved by showing audience the threading support of IPP with examples of multimedia encoding applications. The completion of the module will motivate students to explore the IPP library and to use specific IPP domains that can be applied in applications development. Additionally, IPP may also be used as benchmark or reference for performance implementations.

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1.a.3 Examples of Concurrent Solution Design by S.Y. , November 2008, (link to overview page with further information and links)

Course / Module Description:
This lecture-only module illustrates the parallel solutions by means of discussion and instructor demonstration. The lectures cover the workload partitioning methods for the typical program constructs of iteration, function (call) as well as the sub-tasking application scenario. The examples used in the tudy are known numeric algorithm of Least Square Estimation, encryption algorithm Huffman Coding and implementation of a Spell Checker. The examples in this module will enrich the case study base that are currently in use for standard concurrent/parallel programming curricula.

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1.b.1 Multi-core Architecture & Fundamentals Tools (Compiler & VTune) by B.C., August 2008, (link to overview page with further information and links)

Course / Module Description:
The module with Lab sections introduces how to take advantage of the parallel features of Intel core architecture processors, including utilizing the cores and taking advantages of the SIMD architecture. OpenMP is used to parallelize the applications. VTune and compiler are used to show how "cache effects" can be avoided.

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1.b.2 Parallel Programming Design Patterns by C. B. , July 16th 2008, (link to overview page with further information and links)

Course / Module Description:
This module is based on the book Patterns for Parallel Programming by Timothy G. Mattson, et al. This book discusses the design consideration of a parallel program as a pattern language structure that evolves in four design phases. The teaching aids in the module include discussion questions that encourage knowledge exchange among students, graphical illustration of how different design considerations are addressed in a sample application, and examples and analogies to facilitate understanding.

Content:
The major topics of this module include: – Generic Parallel Algorithms (2 labs) – Task Scheduler (lab) – Highly Concurrent Containers (lab) – Low-level Synchronization Primitives – Scalable Memory Allocation (lab) HW and SW requirements: • Hardware needs • Dual-core or better equipped laptop • Software needs • Appropriate compiler (Windows, Linux) • Intel Threading Building Blocks library

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1.b.3 Threading Building Blocks and Libraries: Intel TBB by C. B. , July 2008, (link to overview page with further information and links)

Course / Module Descrition:
This is a complete courseware module, containing lecture and lab exercises. This module introduces the major components of the Intel® Threading Building Blocks Library – the current official release version 2.0 is featured Content: The major topics of this module include: – Generic Parallel Algorithms (2 labs) – Task Scheduler (lab) – Highly Concurrent Containers (lab) – Low-level Synchronization Primitives – Scalable Memory Allocation (lab)
HW and SW requirements • Hardware needs • Dual-core or better equipped laptop • Software needs • Appropriate compiler (Windows, Linux) • Intel Threading Building Blocks library

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2.a Performance Library: Intel® Math Kernel Library (MKL) by S. Y. , July 2008, (link to overview page with further information and links)

Course / Module Description:
This module gives an introduction to the Intel Math Kernel Library. Topics cover MKL components with features, how to use the libraries and how to link with the libraries into an application for threading applications. Two labs are provided for the use of BLAS (Basic Linear Algebra Subroutines) libraries and Vector Statistical Library.

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3.a Threading Games for Performance July 2008, (link to overview page with further information and links)

Course / Module Description:
This mid-level workshop takes a sample game, Destroy the Castle, from serial to parallel over the course of one day. Strategies are considered for optimal threading of components such as physics, AI, and rendering. Tools are employed to identify workload hotspots, profile threading performance, and trap threading errors such as race conditions. Ample time is dedicated to lab exercises.

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3.b Introduction to Parallel Programming (link to overview page with further information and links)

Course / Module Description:
This course introduces concepts and approaches common to all implementations of parallel programming for shared-memory systems. It offers lectures combined with walk-through labs and hands-on lab exercises. While lab exercises are done on in C using OpenMP*, the concepts apply broadly to any specific threading model.

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3.c Developing Applications for Intel® Multi-Core processors (Microsoft* .NET* Environment) (link to overview page with further information and links)

Course / Module Description:
This course, based on lectures and hands-on exercises provides an introduction to Intel® Multi-Core Architecture and covers a complete overview of the importance of parallelism, threading concepts, threading methodology and Microsoft.NET threading principles. This course also includes an overview of performance analysis for Multi-Core platforms using the Intel® VTune(TM) Performance Analyzer Callgraph & Sampling technology.

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3.d Parallel Architecture for Games (link to overview page with further information and links)

Course / Module Description:
This self-guided module examines a game architecture developed by Intel, designed to take advantage of all CPU cores available within a system. This courseware explores how to support and overcome the challenges of parallelism in the context of a modern game architecture. It also provides a detailed review of the parallel framework on which to build threaded scalable games. After successful completion of the course, the participants will be able to describe a highly parallel game framework that can be fully utilized today and to outline ways to customize this framework for their own use.

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4.a Multi-core Programming for Academia (link to overview page with further information and links; Collection of Courseware modules)

Course / Module Description:
This courseware offers lectures combined with walk-through examples and hands-on lab exercises. It provides an introduction to Intel® Multi-Core Architecture and covers a complete overview of the importance of parallelism, threading concepts, multithreading methodology and programming with threads (Windows*, OpenMP*, Pthreads*). The course also includes an overview of performance analysis for Multi-Core platforms using the latest Intel® threading tools. (Intel Software College offers onsite faculty trainings of this course to selected universities). Link to the Spanish version (NEW) of the material. Thanks to Professor José Luis Elvira Valenzuela from Mexico.

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