Intel's Director of Parallel Software and Tools Sanjiv Shah discusses What's new with vTune?

Dr. Clay Breshears talks with Intel Engineer Werner Krotz Vogel about Intel cluster tools and other SC10 highlights.

Intel Software Architect Dr. Michael McCool talks with Parallel Programming Community Manager Kathy Farrel about Intel® Array Building Blocks.

Dr. Clay Breshears and Intel Technical Consulting Engineer Noah Clemons discuss Particle Physics Track Fitting with Array Building Blocks.

Intel Corporation announced plans to deliver new products based on the Intel® Many Integrated Core (MIC) architecture that will create platforms that could run trillions of calculations per second, while also retaining the benefits of standard Intel processors.

· The first product, codenamed “Knights Corner,” will target Intel’s 22nm process and will use Moore’s Law to scale to more than 50 processing cores on a single chip. Intel® Xeon® processors and Many Integrated Core (MIC) -based products share common tools, software algorithms and programming techniques to support diverse programming models that will place unprecedented performance in the hands of scientists, researchers and engineers.

ARE YOU READY TO TEST YOUR SKILLS IN THIS YEAR'S THREADING CHALLENGE?

Over the last two years the Intel^® Threading Challenge has attracted developers of varying experience, from all over the globe.  That continued participation from the community has driven us to offer a new iteration, with new problems, and a chance to win prizes again this year.  We know you love a good puzzle; so this year our resident experts have agreed to pull together new and interesting problems for you!

Phase 1 Launches (both levels) on Monday May 31, 2010 an 12:00 PM (PDT) and this year's contest will have some similarities to last year but will also have new elements that you should be aware of so get more on those changes below and start threading your way to prizes today!

You will have until June 21, 2010 at 12:00 PM (Pacific Daylight Time) to submit your entry.  Please see official rulesforum for this problem to get your questions answered.  Good Luck!

This year's contest is organized so any level of developer can have the opportunity to participate.  Two levels of participation are available; the Apprentice level gives those just getting started in multithreading development a chance to try out and improve their threading skills, the Master level will be executed similar to last year's contest providing those with more experience a chance to test their skills and compete against other experienced developers.

Intel(R) Threading Building Blocks 3.0 (Intel(R) TBB) is now available for download. This latest release of Intel TBB 3.0 offers extended compatibility support for Microsoft* Visual Studio* 2010 Parallel Patterns Library (PPL) and Concurrency Runtime (ConcRT); new task scheduler features; enhanced performance; and expanded functions.

What's New in Intel TBB 3.0:

Extended Compatibility - provides more choices, interoperability, and compatibility support
- Microsoft* Visual Studio 2010 PPL and ConcRT compatibility and interoperability support
- Microsoft* Windows 7 support
- Apple* Snow Leopard support

Enhanced Task Scheduler Features - more predictable and expanded task scheduling
- Starvation proof scheduling provides fairness-oriented task scheduling for queue-like work
- Master thread isolation improves task scheduling predictability and responsiveness via independent task scheduling for different master threads 
- Improved scheduling of simultaneous task groups from a single master thread via discriminative waits 
- Improved tasks cancellation and exception handling support: task group context can now be created and destroyed in different threads

Enhanced Scalable Memory Allocator
- Scalable memory allocator includes additional optimizations for large blocks (>8KB)

Expanded Use Cases, Classes and Functions - added interoperability and capabilities
- New function parallel_pipeline a strongly typed lambda-friendly interface for building and running pipelines
- New C++0x compatible class condition_variable - portable C++ implementation of POSIX* condition variables
- New container concurrent_unordered_map supports concurrent insertion and traversal with no visible locking
- New synchronization primitive reader_writer_lock - reader-writer mutex that is scalable and gives preference to writers

Improved Documentation - more examples
- Added new Design Patterns documentation that articulates usage models and common patterns

With Intel TBB 3.0 Developers gain the added benefits of a simpler and more rapid way of developing robust parallel applications that scale to available processor cores, compatible with multiple environments, and easier to maintain code.

*Other names and brands may be claimed as the property of others