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Title Modified Date
Intel® compiler options for SSE generation (SSE2, SSE3, SSSE3, SSE4) and processor-specific optimizations
Explains which Intel Compiler switches to use to target and optimize for a specific platform, cpu or processor.
Type: Code
 07/13/2009
Block-Matching In Motion Estimation Algorithms
Introduction The Streaming SIMD Extensions 2 (SSE2) technology introduces new Single Instruction Multiple Data (SIMD) double-precision floating-point instructions and new SIMD integer instruction ...
Type: Code
 01/14/2009
Optimized Matrix Library for use with the Intel® Pentium® 4 Processor's SSE2 Instructions
Introduction On January 2000, Intel published an optimized matrix library (4D single-precision matrix and vector classes) for use with Pentium® III Streaming SIMD (Single Instruction Multiple Data ...
Type: Code
 10/22/2008
SSE2 Instructions in a Double-precision 3D Transform
Inroduction The Streaming SIMD Extensions 2 (SSE2) technology introduces new Single Instruction Multiple Data (SIMD) double-precision floating-point instructions and new SIMD integer instructions ...
Type: Code
 10/03/2008
Using Streaming SIMD Extensions 2 (SSE2)
Introduction The Streaming SIMD Extensions 2 (SSE2) introduces new Single Instruction Multiple Data (SIMD) double-precision floating-point instructions and new SIMD integer instructions into the I ...
Type: Code
 10/03/2008
Using SSE2 to Evaluate a Hidden Markov Model with Viterbi Decoding
Introduction The Streaming SIMD Extensions 2 (SSE2) technology introduces new Single Instruction Multiple Data (SIMD) double-precision floating-point instructions and new SIMD integer instructions ...
Type: Code
 05/07/2008
CPUID for x64 Platforms and Microsoft Visual Studio* .NET 2005
When targeting x64 platforms in Visual Studio .NET* 2005, programmers are no longer able to use inline assembly code as they did for 32-bit code. This forces the programmer to either rely on C/C++ code ...
Author: Eric Palmer (Intel)
Type: Code
 05/07/2008