| May 26, 2010 9:00 AM PDT | |
One of the most valuable features of the Intel IPP library is the instruction set "dispatcher" that is built into the library. This dispatcher automatically executes the optimal version of each IPP function at run time, to match your specific processor type and instruction set. In other words, each IPP function in the library actually consists of multiple "variations on a theme."
Dispatcher For Atom dynamic library
For Intel® Atom Processor, in IPP v6.0 and v6.1 release, we provided only dynamic library. All Intel IPP functions will be dispatched to use "s8" optimized libraries for 32 bit platform and "n8" optimized libraries for Intel® 64 bit platform when you target Intel Atom processors.
32-bit Processor IPP Architecture Codes
- v8 - New Optimizations for 32-bit applications on Intel® CoreTM 2 and Intel® Xeon® 5100 Processors
- s8 - New Optimizations for 32-bit applications on Intel® AtomTM family processors
- see others from Understanding CPU Dispatching in the Intel® IPP Library
64-bit Processor IPP Architecture Codes
- u8 - New Optimizations for 64-bit applications on Intel® CoreTM 2 and Intel® Xeon® 5100 Processors
- n8 - New Optimizations for 64-bit applications on Intel® AtomTM family processor
- see others from Understanding CPU Dispatching in the Intel® IPP Library
For more information, please see these IPP knowledge base articles:
Intel® AtomTM Processors support in Intel IPP
Understanding CPU Optimized Code in the Intel IPP Library
Is There a Function to Detect the Processor Type?
Using IPP on AMD Processors
Smart Dispatcher for Atom/Merom Static library
Starting 7.0, we add static libraries support to Atom/Merom processor. Creating one additional cpu-specific optimization code in static library for Atom/Mero processor would be very space inefficient. Considering both v8 and s8 optimization code are for supplemental SSE3 instructions, we combined v8,s8 (and u8,n8) into a single "smart dispatch" library. Smart dispatcher technology allow to set for the each function which cpu specific optimization will be called for the each CPU type individually, at the same time, it allow to remove the duplicated code from IPP libraries and choose the best optimization code for Atom processor and Merom processor.
IA-32
| v8 | Supplemental SSE3 | Core 2, Xeon® 5100 | |
| s8 | Supplemental SSE3 (compiled for Atom) | Atom |
| u8 | Supplemental SSE3 | Core 2, Xeon® 5100 | |
| n8 | Supplemental SSE3 (compiled for Atom) | Atom |
But please note that the dispatcher is transparent for user. When you call ippInit(), the cpu optimized code is automatically dispatched, you do not need to do anything special for the Atom processor.
See ippInit() in IPP Dispatcher Control Functions - ipp*Init*() functions.
Limitation for the Smart dispatcher technology
1. The smart dispatcher technology is only implemented for static libraries and Atom/Merom processor, both 32bit and Intel 64bit. In the future, we may extend it to dynamic libraries and other processors.
2. Only some special cases can expose the changes:
For instance, ipp_{cpu}.h files contain redefinitions for all IPP functions:
#define ippiAdd_16s_C1RSfs v8_ippiAdd_16s_C1RSfs
#define ippiAdd_16s_C3IRSfs s8_ippiAdd_16s_C3IRSfs
#define ippiAdd_16s_C3RSfs v8_ippiAdd_16s_C3RSfs
Or if user developed one own static dispatcher, it won't work with IPP 7.0 libraries longer, please see Intel® IPP - Intel® IPP linkage models - quick reference guide=>Single processor static linkage
| Optimization Notice |
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |
This article applies to: Intel® Integrated Performance Primitives Knowledge Base
For more complete information about compiler optimizations, see our Optimization Notice.


