An evaluation of the impact of memory configuration on the performance of applications running on Intel® Xeon® processor 5500-series based servers
Optimizing memory configurations of servers using the 5500 series Intel® Xeon® processors is important to optimize bandwidth from the three-channel memory controller. This paper provides information on various memory configurations on 16 HPC applications. Author: Robert Godley (Intel) Type: Technical Article |
10/28/2009
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HowTo – HPL Over Intel MPI
This is a step by step procedure of how to run the High Performance Linpack (HPL)benchmark on a Linux cluster using Intel-MPI. This was done on a Linux cluster of 128 nodes running Intel’s Nehalem processor 2.93 MHz with 12GB of RAM on each node. Author: Mohamad Sindi Type: Technical Article |
10/26/2009
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Performance of MPI cluster applications with Intel(r) HyperThreading Technology
6 HPC cluster applications benchmarked with Intel(r) HyperThreading Technology enabled and disabled on Intel(r) Xeon(r) 5560 CPU cluster Author: Timothy Prince (Intel) Type: Technical Article |
10/13/2009
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Java Application Server Optimization for Multi-core Systems
This paper examines the performance characteristics of Java application servers running on 32-bit and 64-bit Java Virtual Machines (JVM) and operating systems on the latest architectures and platforms available today. Author: Khun Ban (Intel) Type: Technical Article |
10/07/2009
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"Vectorization: Writing C/C++ code in VECTOR Format"
Vectorization: Writing C/C++ code in VECTOR FormatMukkaysh SrivastavComputational Research Laboratories (CRL) - Pune, India
1.0 Introduction: Vectorization has been key optimization principle over ... Author: srimks Type: Technical Article |
10/06/2009
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Running The HPL Benchmark Over Intel MPI
This is a step by step procedure on how to run the High Performance Linpack (HPL) benchmark on a Linux cluster using Intel-MPI. This was done on a Linux cluster of 128 nodes running Intel’s Nehalem processor 2.93 MHz with 12GB of RAM on each node. Author: Mohamad Sindi Type: Technical Article |
09/28/2009
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Intel® compiler options for SSE generation (SSE2, SSE3, SSSE3, SSE4) and processor-specific optimizations
Explains which Intel Compiler switches to use to target and optimize for a specific platform, cpu or processor. Type: Technical Article |
07/13/2009
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Prana Studios leverages Intel® Xeon® Processor 5500 Series to get better 3D animation rendering
Introduction: Prana Studios is a leading Animation house based out of Mumbai and Los Angeles. Prana's core business is focused on four main areas: Long-form CG content, location based entertainment, g ... Author: Preethi Raj (Intel),Udaysimha Mysore (Intel),Rama Kishan Malladi (Intel) Type: Technical Article |
07/08/2009
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High Clocks Per Instruction Retired when vectorizing the loop.
Sometimes when we vectorize a loop, we get a high Clocks Per Instruction Retired (CPI) value. This happens when there is high bus utilization and the bus gets saturated. Type: Technical Article |
11/18/2008
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Developing for Speed: A Four-Step Approach
by George Walsh
Introduction
There's really no denying that application optimization yields performance benefits. The question in each case is whether time spent optimizing and resulting perform ... Author: gbwalsh Type: Technical Article |
10/20/2008
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AP949 Using Spin Loops on Intel® Pentium® 4 Processor and Intel Xeonr Processor
Parallel programs with multiple threads must use synchronization techniques in order to insure correct operation. Generally, synchronization operations use shared synchronization variables and "s ... Type: Technical Article |
05/13/2008
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Cache Blocking Technique on Hyper-Threading Technology Enabled Processors
by Phil Kerly
Introduction
Hyper-Threading Technology-enabled processors contain multiple logical processors per physical processor package. The state information necessary to support each logical pr ... Author: Philip Kerly (Intel) Type: Technical Article |
07/18/2007
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Hyper-Threading Technology: Impact on Compute-Intensive Workloads
Intel's recently introduced Hyper-Threading Technology promises to increase application- and system-level performance through increased utilization of processor resources. It achieves this goal by al ... Author: Sanjiv Shah (Intel),William Magro (Intel),Paul Petersen (Intel) Type: Technical Article |
05/25/2007
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Extending the World's Most Popular Processor Architecture
Introduction
Intel has a long history of innovation in adding new capabilities to computer architecture and enabling the industry to deliver advanced applications with greater performance and capa ... Type: Technical Article |
09/27/2006
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Adjusting Thread Stack Address To Improve Performance on Intel® Xeon® Processors
by Phil KerlySenior Software EngineerIntel Corporation, Architecture Performance Engineering
Introduction
Intel® Xeon® processors with Hyper-Threading Technology enabled contain multiple logical proc ... Author: Philip Kerly (Intel) Type: Technical Article |
06/12/2006
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Dual vs. Multiprocessor chips: What's the difference?
by Andrew Binstock
Introduction
In late 2001, early 2002, two processor families based on the Intel NetBurst® microarchitecture were introduced: the Pentium® 4 and the Intel® Xeon® processor fami ... Author: Andrew Binstock Type: Technical Article |
12/21/2005
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