A simple example to measure the performance of an Intel® MKL function
The time required by the first MKL call should be ignored for the perfromance measurements. The first MKL call has overhead due to buffer allocation and thread initialization. Ignoring the first MKL call gives more consistent times for small problems. Type: Technical Article |
MKL intel mkl GEMM BLAS matrix multiplication small matrix Intel MKL Performance |
04/27/2012
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Intel® Performance Counter Monitor - A better way to measure CPU utilization
The Intel® Performance Counter Monitor provides sample C++ routines and utilities to estimate the internal resource utilization of the latest Intel® Xeon® and Core™ processors and gain a significant performance boost. Type: Technical Article |
monitoring Intel Performance Counter Monitor simultaneous multithreading out-of-order execution Intel® Performance Counter Monitor Intel® Xeon® Core™ processors multi-level caches pipelining |
04/13/2012
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HowTo – HPL Over Intel MPI
This is a step by step procedure of how to run the High Performance Linpack (HPL)benchmark on a Linux cluster using Intel-MPI. This was done on a Linux cluster of 128 nodes running Intel’s Nehalem processor 2.93 MHz with 12GB of RAM on each node. Type: Technical Article |
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08/08/2011
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Compile and run MPIBLAST 1.6.0 in the Intel(R) Cluster Ready Reference Design S5520UR-ICR1.1-ROCKS5.3-CENTOS5.4-C2 v1.0
Prerequisites
You need to have deployed the latest Intel(R) Cluster Ready Reference Design S5520UR-ICR1.1-ROCKS5.3-CENTOS5.4-C2 v1.0.This reference design targets the next components:
Intel® Xeon® ... Type: Technical Article |
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07/07/2011
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Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSE3_ATOM, SSSE3, SSE4.1, SSE4.2, AVX, AVX2) and processor-specific optimizations
Explains which Intel® Compiler switches to use to target and optimize for a specific platform, microarchitecture, CPU or processor. Type: Technical Article |
dual-core xeon pentium SSE2 SSE3 SSE Core 2 Duo SSE4.2 SSSE3 SSE4.1 MMX Core 2 Quad atom Core i7 compiler AVX vcsource_domain_media vcsource_os_windows vcsource_platform_desktoplaptop vcsource_domain_graphics vcsource_product_icc vcsource_index |
09/02/2010
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Superscalar programming 101 (Matrix Multiply) Part 4 of 5
In the last installment (Part 3) we saw the effects of the QuickThread Parallel Tag Team method of Matrix Multiplication performed on two single processor systems:
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Where the Intel Q6600 (4 co ... Type: Technical Article |
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08/27/2010
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Superscalar programming 101 (Matrix Multiply) Part 5 of 5
In part 4 we saw the effects of the QuickThread Parallel Tag Team Transpose method of Matrix Multiplication performed on a Dual Xeon 5570 systems with 2 sockets and two L3 caches, each shared by four c ... Type: Technical Article |
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08/25/2010
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Improving Medical Imaging Performance on the Intel® Xeon® Processor 5500 series
In Medical Imaging, it is important to maximize healthcare quality by providing the best images in the shortest time to assure accurate diagnosis & patient treatment. This article describes the 50x speedup of an image reconstruction algorithm. Type: Technical Article |
Vtune Xeon 5500 visual computing medical imaging image reconstruction MRI SPECT vcsource_type_techarticle vcsource_domain_media vcsource_os_windows vcsource_platform_desktoplaptop vcsource_product_vtunexe vcsource_product_icc vcsource_os_linux vcsource_index |
07/12/2010
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The Cost Benefit Case for Database Migration to Intel Servers
Although server consolidation has become pervasive, to date it has been more commonly applied to application and infrastructure servers, rather than database servers. This report examines the cost savings by upgrading and consolidating IBM DB2 databases. Type: Technical Article |
xeon Xeon 5500 xeon 5500 series DB2 database |
11/11/2009
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An evaluation of the impact of memory configuration on the performance of applications running on Intel® Xeon® processor 5500-series based servers
Optimizing memory configurations of servers using the 5500 series Intel® Xeon® processors is important to optimize bandwidth from the three-channel memory controller. This paper provides information on various memory configurations on 16 HPC applications. Type: Technical Article |
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10/28/2009
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Java Application Server Optimization for Multi-core Systems
This paper examines the performance characteristics of Java application servers running on 32-bit and 64-bit Java Virtual Machines (JVM) and operating systems on the latest architectures and platforms available today. Type: Technical Article |
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10/07/2009
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"Vectorization: Writing C/C++ code in VECTOR Format"
Vectorization: Writing C/C++ code in VECTOR FormatMukkaysh SrivastavComputational Research Laboratories (CRL) - Pune, India
1.0 Introduction: Vectorization has been key optimization principle over ... Type: Technical Article |
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10/06/2009
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Running The HPL Benchmark Over Intel MPI
This is a step by step procedure on how to run the High Performance Linpack (HPL) benchmark on a Linux cluster using Intel-MPI. This was done on a Linux cluster of 128 nodes running Intel’s Nehalem processor 2.93 MHz with 12GB of RAM on each node. Type: Technical Article |
High Performance Linpack HPL Nehalem MKL Intel MPI Compiler GFLOPS Mohamad Sindi |
09/28/2009
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Prana Studios leverages Intel® Xeon® Processor 5500 Series to get better 3D animation rendering
Introduction: Prana Studios is a leading Animation house based out of Mumbai and Los Angeles. Prana's core business is focused on four main areas: Long-form CG content, location based entertainment, ga ... Type: Technical Article |
xeon India Case Study Prana Studios Xeon case study vcsource_os_windows vcsource_type_news vcsource_domain_graphics vcsource_index |
07/08/2009
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High Clocks Per Instruction Retired when vectorizing the loop.
Sometimes when we vectorize a loop, we get a high Clocks Per Instruction Retired (CPI) value. This happens when there is high bus utilization and the bus gets saturated. Type: Technical Article |
simd SSE2 SSE3 SSE4 SSE High CPI Vectorizer hardware prefetcher SSE1 Memoray latency BUS Saturation Vtune |
11/18/2008
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Developing for Speed: A Four-Step Approach
by George Walsh
Introduction
There's really no denying that application optimization yields performance benefits. The question in each case is whether time spent optimizing and resulting perfor ... Type: Technical Article |
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10/20/2008
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AP-949 Using Spin Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor
Parallel programs with multiple threads must use synchronization techniques in order to insure correct operation. Generally, synchronization operations use shared synchronization variables and "spin-wa ... Type: Technical Article |
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05/13/2008
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Cache Blocking Technique on Hyper-Threading Technology Enabled Processors
by Phil Kerly
Introduction
Hyper-Threading Technology-enabled processors contain multiple logical processors per physical processor package. The state information necessary to support each logical pr ... Type: Technical Article |
Hyper-Threading Multi-threading cache blocking netburst |
07/18/2007
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Hyper-Threading Technology: Impact on Compute-Intensive Workloads
Intel's recently introduced Hyper-Threading Technology promises to increase application- and system-level performance through increased utilization of processor resources. It achieves this goal by al ... Type: Technical Article |
OpenMP Hyper-Threading xeon Multi-threading |
05/25/2007
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Extending the World's Most Popular Processor Architecture
Introduction
Intel has a long history of innovation in adding new capabilities to computer architecture and enabling the industry to deliver advanced applications with greater performance and cap ... Type: Technical Article |
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09/27/2006
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Adjusting Thread Stack Address To Improve Performance on Intel® Xeon® Processors
by Phil KerlySenior Software EngineerIntel Corporation, Architecture Performance Engineering
Introduction
Intel® Xeon® processors with Hyper-Threading Technology enabled contain multiple logical proc ... Type: Technical Article |
Multi-threading xeon C++ Compiler |
06/12/2006
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Dual vs. Multiprocessor chips: What's the difference?
by Andrew Binstock
Introduction
In late 2001, early 2002, two processor families based on the Intel NetBurst® microarchitecture were introduced: the Pentium® 4 and the Intel® Xeon® processor fami ... Type: Technical Article |
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12/21/2005
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