4,580 Posts served
11,094 Conversations started
- Academic

- Android

- Art, Music, & Animation

- Embedded Computing

- Events

- Game Development

- Graphics & Media

- Intel SW Partner Program

- Intel® AppUp Developer Program

- Manageability & Security

- Mobility

- Open Source

- Parallel Programming

- Performance and Optimization

- Power Efficiency

- Server

- Site News & Announcements

- Software Tools

- Ultrabook

- Association for Computing Machinery TechNews (ACM)
- Go Parallel! (Dr. Dobbs)
- HPCwire (Tabor Communications, Inc.)
- insideHPC (John West)
- Joe Duffy's Weblog (Microsoft)
- Microsoft Parallel Programming Development Center (Microsoft Germany)
- MultiCoreInfo.com
- scalability.org (Scalable Informatics)
- Software Dev Blog (Intel Germany)
- Soft Talk Blog (Intel United Kingdom)
- The Moth (Microsoft)
GCDC’08: Intel gets ready for Nehalem
By Michael J Huelskoetter (90 posts) on August 14, 2008 at 7:19 am
Three days ago Intel heralded a new processor era when they officially announced their next microarchitecture which is known under the codename „Nehalem“. The brand will be named Intel Core processor with its first product being the Intel Core i7.
Besides many new features like seven additional SSE4 instructions, multi-level shared cache and enhanced branch prediction there are two major improvements which turn Nehalem into a completely new microarchitecture:
Massive scalability: At runtime, Nehalem manages cores, threads, caches, interfaces and power dynamically. As a consequence power consumption and performance will always be perfectly balanced. This means, if you need more computing power the needed watts won‘t increase. On the other hand, you can reduce power consumption to its minimum while there’s still enough performance left for ambitious applications.
New memory interface: While Intel processors became faster and faster, memory interconnections turned out to be the real bottleneck in a high-performance computer. But this is a problem that belongs in the past: with Intel QuickPath Architecture enormous data can be transfered through the computing system with almost no limitations. In order to accomplish this Intel removed the North Bridge which connected the CPU with the memory system.
Instead of an external chip, Nehalem based processors will have an integrated memory controller which is capable of transferring data with 32 GB/s max between RAM and CPU. At the same time Intel created direct interconnections between all components with a maximum transfer rate of 25,6 GB/s. This means that processors can exchange data directly or with other I/O components. These fast data transactions will be additionally supported by intelligent caches which will further minimize latencies.
If you want to learn more about Intel Core microarchitecture aka Nehalem just visit the dedicated Intel webpage where you find multimedia demos, white papers and podcasts. But you can also come to GCDC'08 and have a look at the Intel Nehalem demo.
Categories: Events, Parallel Programming
Tags: gcdc
For more complete information about compiler optimizations, see our Optimization Notice.

