From the labs: Single-chip Cloud Computer

By Sean Koehl (Intel) (6 posts) on December 2, 2009 at 3:32 pm

I just returned from a San Francisco press event where our CTO Justin Rattner announced our latest many-core research chip, which we call a "single-chip cloud computer," or SCC for short. It was an exciting event, with not only a briefing but a set of six demonstrations of applications that our researchers have already ported to this 48 IA-core experimental chip, including one from Microsoft researchers who have modified Visual Studio to program apps for the many-core processor.

The anatomy of the SCC

The anatomy of the SCC


In short, this chip is purely for research purposes, but represents a new direction as multi-core scales to many. The architecture resembles a network of computers as you would find in the cloud, hence the name. The cores are connected by a high bandwidth mesh network an can each boot their own OS and software stack and communicate via message passing. So, to a programmer it resembles a cluster. That allows us to try out proven, highly parallel datacenter and HPC programming models at the chip level, both to give us insight into making better chips for the cloud as well as generally to find newer and better ways to scale our mainstream processors for the next decade and beyond.

Jim Held, the Intel Fellow in charge of our Tera-scale Research Program has written a blog explaining the motivation behind developing this chip and what it means for software research. He's actually in China at the moment, and will be briefing press there on the chip in about 45 minutes. I encourage you to take a look at his post, as well as this youtube video that features some of the researchers who led the hardware and software design for the chip.

Another notable thing about this chip is that we will be sharing a few dozen of our SCC systems with research collaborators in industry and academia. We've already began speaking to a few, including Microsoft, UC Berkeley, the University of Illinois, Carnegie Mellon University, and ETH Zurich. We're developing a program to form a community around the chip. If you happen to be a researcher and think your institution might qualify, we've set up an application form where you can express your interest.

Categories: Academic, Parallel Programming, Uncategorized
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For more complete information about compiler optimizations, see our Optimization Notice.

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