I'm headed to Hamburg Germany for the International Supercomputing Conference next week.
We will be talking a lot about our Many-Integrated Core (MIC) Architecture and how to realize amazing performance on highly parallel applications.
We have some incredible demos and partners in our booth - so I hope you can drop by to visit us.
Of course, I'll be helping with demos that show our many programming methods and tools to help for both our multicore processors and our many-core co-processors (MIC architecture).
Drop by and say hello if you can - Intel booths 530 and 801.
We will be talking a lot about our Many-Integrated Core (MIC) Architecture and how to realize amazing performance on highly parallel applications.
We have some incredible demos and partners in our booth - so I hope you can drop by to visit us.
Of course, I'll be helping with demos that show our many programming methods and tools to help for both our multicore processors and our many-core co-processors (MIC architecture).
Drop by and say hello if you can - Intel booths 530 and 801.
Comments
ISC was amazing... and we got to show off some very impressive results around MIC - in particular customers with exciting results on the earliest protoype hardware. Here are four videos that InsideHPC posted based on their tour of our demos:
CERN HLT Analysis of Intel Knights Ferry on High Energy Physics: In this video, CERN demonstrates performance results from prototype Intel Knights Ferry hardware on its high energy physics applications. Recorded at the ISC’11 conference in Hamburg, June 21, 2011. http://insidehpc.com/2011/07/12/video-cern-hlt-analysis-of-intel-knights-ferry-on-high-energy-physics/
Molecular Dynamics Linear Speedup on Intel Knights Ferry: In this video, Intel’s Byeung Choe demonstrates linear speedups on Knights Ferry on Molecular Dynamics. Recorded at the ISC’11 conference in Hamburg, June 21, 2011. http://insidehpc.com/2011/07/11/demo-video-linear-speedup-on-intel-knights-ferry/
Intel MIC Port of TifaMMy, a Cache-oblivious Matrix-matrix Multiplication: In this video, Alexander Heinecke from the Technical University of Munich demonstrates the advantages of the Intel MIC architecture for TifaMMy, a cache-oblivious Matrix-matrix Multiplication code. Recorded at the Intel booth at ISC’11 in Hamburg on June 20, 2011. http://insidehpc.com/2011/07/08/video-intel-mic-port-of-tifammy-a-cache-oblivious-matrix-matrix-multiplication/
Video: Better Together – Intel Demo Shows Application Speedups with Xeon & Knights Ferry: In this video, I described our Hybrid Computing demo at ISC’11. Using prototype Knights Ferry accelerators along with Intel Xeon processors provides significant speedups on highly parallel code. Since Knights Ferry uses X86 cores, it also offers a rich programming environment. http://insidehpc.com/2011/07/07/video-better-together-intel-demo-shows-application-speedups-with-xeon-knights-ferry/