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Optimizing Software Applications for NUMA: Part 7 (of 7)

By David Ott (Intel) (34 posts) on May 18, 2011 at 7:12 am
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Summary NUMA, or Non-Uniform Memory Access, is a shared memory architecture that describes the placement of main memory modules with respect to processors in a multiprocessor system. The advantage of the NUMA architecture as a hierarchical shared memory scheme is its potential to improve average case access time through the introduction of fast, local memory. [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, optimization, performance

Optimizing Software Applications for NUMA: Part 6 (of 7)

By David Ott (Intel) (34 posts) on May 16, 2011 at 9:31 am
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3.3 Data Placement Using Explicit Memory Allocation Directives Another approach to data placement in NUMA-based systems is to make use of system APIs that explicitly configure the location of memory page allocations. An example of such APIs is the libnuma library for Linux.[1] Using the API, a programmer may be able to associate virtual memory [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, optimization, performance

Optimizing Software Applications for NUMA: Part 5 (of 7)

By David Ott (Intel) (34 posts) on May 11, 2011 at 2:50 pm
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3.2. Data Placement Using Implicit Memory Allocation Policies In the simple case, many operating systems transparently provide support for NUMA-friendly data placement. When a single-threaded application allocates memory, the processor will simply assign memory pages to the physical memory associated with the requesting thread’s node (CPU package), thus insuring that it is local to the [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, optimization, performance

Optimizing Software Applications for NUMA: Part 4 (of 7)

By David Ott (Intel) (34 posts) on May 9, 2011 at 4:29 pm
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3. Strategies for NUMA Optimization Two key notions in managing performance within the NUMA shared memory architecture are processor affinity and data placement. 3.1. Processor Affinity Affinity refers to the persistence of association with a particular resource instance, despite the availability of another instance for the same purpose. Consider the case of processor affinity. Today’s [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, optimization, performance

Optimizing Software Applications for NUMA: Part 3 (of 7)

By David Ott (Intel) (34 posts) on May 5, 2011 at 1:27 pm
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2. NUMA Advantages and Risks The advantage of the NUMA shared memory architecture is its potential to reduce memory access time in the average case. By providing each node with its own local memory, memory accesses can take place in parallel and avoid throughput limitations and contention issues associated with a shared memory bus. In [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, performance

Optimizing Software Applications for NUMA: Part 2 (of 7)

By David Ott (Intel) (34 posts) on May 2, 2011 at 9:16 am
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Modern Processors Modern multiprocessor systems mix these basic architectures as seen in the following diagram: In this complex hierarchical scheme, processors are grouped by their physical location on one or the other multi-core CPU package or “node”. Processors within a node share access to memory modules as per the UMA shared memory architecture. At the [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, performance

Optimizing Software Applications for NUMA: Part 1 (of 7)

By David Ott (Intel) (34 posts) on April 28, 2011 at 8:20 am
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1. The Basics of NUMA NUMA, or Non-Uniform Memory Access, is a shared memory architecture that describes the placement of main memory modules with respect to processors in a multiprocessor system. Perhaps the best way to understand NUMA is to compare it with its cousin UMA, or Uniform Memory Access. In the UMA memory architecture, [...]

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Category: Performance and Optimization
Tags: Memory, NUMA, optimization, performance

Optimizing Software Applications for Power: Part 13 (of 13)

By David Ott (Intel) (34 posts) on December 22, 2010 at 12:57 pm
Comments (1)

Part 13: Example 3 (Maximizing Idle Periods) - Batch I/O requests Frequent I/O operations represent another pitfall in programming for energy efficiency. Frequent, small reads and writes generate a chain of interrupts that work to limit the size and number of idle periods on the system. For example, frequent reads using a small data buffer [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 12 (of 13)

By David Ott (Intel) (34 posts) on December 21, 2010 at 8:28 am
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Part 12: Example 2 (Maximizing Idle Periods) - Avoid polling and busy wait loops Another undesirable program construct is the tight polling loop. “Tight” refers to iteration frequency and the desire to commence subsequent processing immediately after a particular condition has been detected. As with high-resolution periodic timers, the effect for power management is to [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 11 (of 13)

By David Ott (Intel) (34 posts) on December 20, 2010 at 9:40 am
Comments (1)

Part 11: Example 1 (Maximizing Idle Periods) - Avoid high-resolution periodic timers High resolution timers (less than 10 or 15 ms) generate frequent, periodic interrupts that the OS must handle to determine whether a timeout has occurred. While high-resolution timers may seem to be a desirable system feature, in fact, such timers repeatedly wake the [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 10 (of 13)

By David Ott (Intel) (34 posts) on December 16, 2010 at 3:03 pm
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Part 10: Maximizing Idle Periods Beyond reducing computation, developers can improve power management efficiency by thinking carefully how their applications can be structured to avoid reducing system idle periods. As described previously, such idle periods give the OS opportunity to apply power-saving C-states. The longer the idle period, the deeper the C-state. The deeper the [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 9 (of 13)

By David Ott (Intel) (34 posts) on December 14, 2010 at 7:57 am
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Part 9: Example 3 (Reducing Computation) - Compile with optimizations Optimizing compilers are available for almost every programming language in widespread use today. It is something of a curiosity, then, that many programs do not make more use of them, or at least exercise some of the more sophisticated options available on common compilers. Developers [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 8 (of 13)

By David Ott (Intel) (34 posts) on December 13, 2010 at 9:37 am
Comments (1)

Part 8: Example 2 (Reducing Computation) - Reduce data size The amount of computation performed is not only a function of the algorithm used, but of the input data size to which it will be applied. Consider, for example, an image archive and browsing application. Search, comparison, and browsing operations might make use of lower [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 7 (of 13)

By David Ott (Intel) (34 posts) on December 10, 2010 at 7:57 am
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Part 7: Example 1 (Reducing Computation) - Improve algorithmic efficiency As Computer Science graduates know, there is a difference between getting the job done and getting it done efficiently. The canonical example cited in many computational complexity textbooks is that of sorting algorithms. Naïve sorting algorithms can iterate through an array of numbers repeatedly in [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 6 (of 13)

By David Ott (Intel) (34 posts) on December 9, 2010 at 1:59 pm
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Part 6: Reducing Computation As simple as it sounds, a key strategy for reducing application power requirements is to do less computation. With respect to the ACPI framework described above, such reductions have the effect of increasing system idleness and hence OS opportunities for applying power-saving C-states. Reducing computation also decreases processor utilization which allows [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 5 (of 13)

By David Ott (Intel) (34 posts) on December 7, 2010 at 7:45 am
Comments (1)

Part 5: Strategies for Application Power Optimization Discussion up to this point has reviewed the ACPI framework, including the manner in which hardware platform features (C-states, P-states) and the operating system (OSPM) conspire to manage system power. The question now becomes, “What can application developers do to play into this power management framework?” Said another [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 4 (of 13)

By David Ott (Intel) (34 posts) on December 6, 2010 at 8:56 am
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Part 4: Operating System Power Management (OSPM) A distinctive highlight of ACPI is the shift from BIOS-controlled power management in APM to operating system power management, or OSPM. Several reasons underlie this shift. First, the complexity requirements for power management have continued to grow and BIOS-based solutions increasingly pose integration difficulties with operating systems running [...]

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Category: Power Efficiency, Uncategorized
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 3 (of 13)

By David Ott (Intel) (34 posts) on December 3, 2010 at 3:09 pm
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Part 3: Hardware-Software Interface ACPI describes itself as neither a software specification nor a hardware specification. Rather, it is an interface specification addressing both components and how they should interact with one another.[1] As such, several elements serve to bridge the gap between hardware features and software management control. ACPI system description tables describe the [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 2 (of 13)

By David Ott (Intel) (34 posts) on December 3, 2010 at 3:03 pm
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Part 2: Hardware Platform Power States On a hardware platform level, ACPI defines a set of power states pertaining to various aspects of the system: global system states (Gx) like “off” and “working”, sleep states (Sx), device power states (Dx), processor power states (Cx), device and processor performance states (Px), and throttling states (Tx). Of [...]

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Category: Power Efficiency
Tags: ACPI, optimization, Power Efficiency, software

Optimizing Software Applications for Power: Part 1 (of 13)

By David Ott (Intel) (34 posts) on November 29, 2010 at 11:04 am
Comments (1)

Part 1: Power Management Basics Because of the need to integrate hardware features with software management, today’s computer system power management framework is defined by an open industry specification known as ACPI. ACPI, or the Advanced Configuration and Power Interface specification[1], is an operating system-based scheme for managing system power features and is intended to [...]

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Category: Power Efficiency

Trusted Computing and the Enterprise Software Ecosystem: Part 7 (of 7)

By David Ott (Intel) (34 posts) on November 23, 2010 at 10:19 am
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Part 7: Enterprise Security Applications While trusted computing represents a significant step forward in insuring an uncompromised software environment, it should not be understood as a replacement for the many other security applications protecting a user's platform. The distinction to be noted here is that trusted computing measures the software environment to determine whether it [...]

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Category: Manageability & Security
Tags: Enterprise, security, software, trusted computing, TXT, Virtualization

Trusted Computing and the Enterprise Software Ecosystem: Part 6 (of 7)

By David Ott (Intel) (34 posts) on November 22, 2010 at 9:20 am
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Part 6: Implications for Software Developers: Cloud Management Software While the scope of trusted computing may seem limited to an individual computer, one might also consider the broader context of public or private data centers and cloud computing. Among a data center's hosting options might be that of trusted hosting arrangements in which particular clients [...]

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Category: Manageability & Security
Tags: Enterprise, security, software, trusted computing, TXT, Virtualization

Trusted Computing and the Enterprise Software Ecosystem: Part 5 (of 7)

By David Ott (Intel) (34 posts) on November 12, 2010 at 9:16 am
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Part 5: Implications for Software Developers: Operating Systems and Hypervisors The key challenge for operating system and hypervisor designers is to develop systems that build upon TCG principles and Intel® TXT to launch in a trusted manner, thus insuring the integrity of key software components underlying system management and services. In Intel® TXT parlance, such [...]

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Category: Manageability & Security
Tags: Implications for Software Developers: Operating Systems and Hypervisors

Trusted Computing and the Enterprise Software Ecosystem: Part 4 (of 7)

By David Ott (Intel) (34 posts) on November 8, 2010 at 12:45 pm
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Part 4: Intel® TXT So where does Intel fit into the picture? Intel® Trusted Execution Technology (Intel® TXT)[8] is Intel's flagship technology for making possible the implementation of the trusted computing vision described above. TXT, as a collection of technologies, is quite complex, but a summarizing list of features is as follows9: • Processor extensions [...]

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Category: Manageability & Security
Tags: Enterprise, security, software, trusted computing, TXT, Virtualization

Trusted Computing and the Enterprise Software Ecosystem: Part 3 (of 7)

By David Ott (Intel) (34 posts) on November 3, 2010 at 4:06 pm
Comments (1)

Part 3: The Trusted Platform Module (TPM) The TPM, as defined by TCG[7], is a multi-function hardware unit solving a number of problems related to the context of trusted computing. In simplistic terms, the TPM can be thought of as a cryptographic co-processor with a secure integrity measurement storage scheme. The cryptographic co-processor implements the [...]

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Category: Manageability & Security
Tags: Enterprise, security, software, trusted computing, TXT, Virtualization

Trusted Computing and the Enterprise Software Ecosystem: Part 2 (of 7)

By David Ott (Intel) (34 posts) on October 28, 2010 at 1:25 pm
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1.1 Trusted Computing Group The problem of trust in computing platforms has been directly addressed by the Trusted Computing Group (TCG)[2], an industry consortium formed in 2003 to create standards “with the aim of enhancing the security of the computing environment in disparate computer platforms.”[3] TCG defines the notion of trust as “the expectation that [...]

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Category: Manageability & Security
Tags: Enterprise, security, software, trusted computing, TXT, Virtualization

Trusted Computing and the Enterprise Software Ecosystem: Part 1 (of 7)

By David Ott (Intel) (34 posts) on October 21, 2010 at 8:03 am
Comments (8)

Part 1. Trusted Computing Basics It is almost surprising to think how accustomed we’ve grown to the threat of malicious software attacks in this era of rapidly maturing computer technology. Known more broadly as malware, malicious software may take the form of computer viruses, worms, Trojan horses, logic bombs, rootkits, backdoors, bots, keystroke loggers, crimeware, [...]

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Category: Manageability & Security
Tags: Enterprise, security, software, trusted computing, TXT, Virtualization

Does my product support Intel VT?

By David Ott (Intel) (34 posts) on April 2, 2010 at 4:00 pm
Comments (5)

There have been quite a number of questions on the Virtualization and Software Development Forum about whether processor X supports VT-x or chipset Y supports VT-d. A good example is a user who wondered about Intel VT support for processor E8400 CPU and motherboard GigaByte EP31-DS3L Rev 1. A Web site every user should know [...]

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Category: Manageability & Security

Client Virtualization: Who, when, and why?

By David Ott (Intel) (34 posts) on December 15, 2009 at 5:32 pm
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I'd like to pose an open-ended question for interested readers to comment on. Much of the discussion I've heard surrounding virtualization technologies over the past few years pertains to servers. What about client virtualization? Q: Do you think client virtualization will catch on? Who, when, and why? Who? What sectors do you think will lead [...]

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Category: Manageability & Security
Tags: Virtualization, VT-c

Understanding VT-c: Virtualization Technology for Connectivity

By David Ott (Intel) (34 posts) on September 30, 2009 at 5:32 pm
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A number of questions on the Intel Virtualization and Software Development Forum have come up on the topic of VT-c, so perhaps it's time for a blog entry on the subject. Intel Virtualization Technology for Connectivity, or VT-c, is a collection of technologies that improve the performance of network I/O on a virtualized system. VT-c [...]

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Category: Manageability & Security

Virtualization and Performance: Understanding VM Exits

By David Ott (Intel) (34 posts) on June 25, 2009 at 3:14 pm
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VM exits in response to certain instructions and events (e.g., page fault) are a key source of performance degredation in a virtualized systems. But have you ever wondered why? What exactly happens during a VM exit anyway? A VM exit marks the point at which a transition is made between the VM currently running and [...]

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Category: Manageability & Security
Tags: Virtualization, VM exit

Understanding VT-d: Intel Virtualization Technology for Directed I/O

By David Ott (Intel) (34 posts) on June 25, 2009 at 3:13 pm
Comments (4)

I've received a fair number of questions on the Intel Virtualization and Software Development Forum about VT-d -- enough to justify a few words on this note in the blogging sphere. "VT-d" stands for "Intel Virtualization Technology for Directed I/O". The relationship between VT and VT-d is that the former is an "umbrella" term referring [...]

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Category: Manageability & Security
Tags: Virtualization, VT, VT-d

Virtualization and Performance: VM Time Drift

By David Ott (Intel) (34 posts) on June 25, 2009 at 3:13 pm
Comments (1)

An important issue to be aware of when measuring application performance on a virtualized system is that of time drift. A key responsibility of every VMM (hypervisor) is distributing clock ticks generated by the hardware to each VM (guest OS) running on the system. Likewise, it is the responsiblity of each VM to process that [...]

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Category: Manageability & Security
Tags: performance, Virtualization

Web References on Intel Virtualization Technology

By David Ott (Intel) (34 posts) on March 30, 2009 at 9:36 am
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Every so often people ask me for references on Intel virtualization technology. Below are a few helpful links that have served me well, whether it's getting broadly clued in on a technology like VT-d or looking up the particulars of MSR bit semantics. A good starting point for all things virtual at Intel is: http://www.intel.com/technology/platform-technology/virtualization/ [...]

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Category: Manageability & Security
Tags: intel vt, Virtualization, web references