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Archives
Posts from Shannon Cepeda (Intel) 
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Shannon Cepeda has a BS and an MS in Computer Science from North Carolina State University. She has worked for Intel for approximately 10 years, all in roles dealing with performance analysis. She has worked on servers as well as client systems, and hardware/system performance tuning as well as software. |
Minimize frustration and maximize tuning effort with Amdahl's Law
By Shannon Cepeda (Intel) (19 posts) on April 5, 2012 at 11:28 am
Comments (0)
I recently had a question from a customer who had introduced a succesful optimization to a hot function in his application, but did not see as much improvement in the overall application as he expected. This is a fairly common occurence in the iterative process of performance tuning. Usually it happens for one of two [...]
Category: Parallel Programming
Tags: "VTune Amplifier XE", performance tuning, vectorization
Vectorization Series, Part 3 - What are the Benefits?
By Shannon Cepeda (Intel) (19 posts) on February 24, 2012 at 11:48 am
Comments (0)
This will be the final post in my planned short vectorization series. Although I reserve the right to post more on vectorization in the future! In the first post on this topic, I explained that vectorization was parallelism inside a single CPU core, achieved by applying a CPU instruction to multiple data elements at once. [...]
Category: Parallel Programming
Tags: Cilk Plus, Composer XE, Intel Cilk Plus, Intel Compiler, performance optimization, simd, vectorization
Vectorization Series, Part 2- Who Can Use It?
By Shannon Cepeda (Intel) (19 posts) on February 13, 2012 at 2:26 pm
Comments (0)
In my last blog, I introduced the concept of vectorization, which is parallelism across data elements in a register inside a single CPU core. It's a topic that I am very excited about this year, and in this blog I will expand on the subject to address what types of applications can take advantage of [...]
Category: Parallel Programming
Tags: AVX, Intel Cilk Plus, SSE, vectorization, webinar
Vectorization - Find out what it is, Find out More!
By Shannon Cepeda (Intel) (19 posts) on January 31, 2012 at 9:58 am
Comments (4)
One of my performance focus areas for this year is vectorization. I am excited to start creating more content and spreading the message about this technology, as it has been a little bit underappreciated in the past. So to kick things off, I am going to launch a blog series and a 1-hour overview webinar. [...]
Category: Parallel Programming
Tags: MIC, performance, simd, vectorization, webinar
Looking Ahead to 2012
By Shannon Cepeda (Intel) (19 posts) on December 21, 2011 at 9:58 am
Comments (3)
Well, I reflected on 2011 in my last blog, so now it's time to look ahead. My basic role will remain unchanged - I help users of our Intel® Software Development Products to achieve better performance on their applications. I will still be updating our training materials and videos for the latest mainstream Intel processors. [...]
Category: Parallel Programming
Tags: Intel Cilk Plus, Intel Many Integrated Core, Intel MIC
My 5 Favorite New Intel® Software Development Product Features of 2011
By Shannon Cepeda (Intel) (19 posts) on December 16, 2011 at 10:41 am
Comments (2)
It's been a big year for us in the Intel Developer Products Division. We released Intel® Cluster Studio XE and Intel® Parallel Studio XE Service Pack 1. We continued to plan and design our products to provide support for the compute continuum. And of course we worked to grow our community of developers. Throughout the [...]
Category: Parallel Programming
Tags: Intel Cilk Plus, Intel Cluster Studio XE, Intel Software Development Products, Intel VTune Amplifier XE, TBB, TBB 4.0, Threading Building Blocks
Some Performance Advantages of Using a Task-Based Parallelism Model
By Shannon Cepeda (Intel) (19 posts) on December 8, 2011 at 5:30 pm
Comments (3)
As part of my focus on software performance, I also support and consult on implementing scalable parallelism in applications. There are many reasons to implement parallelism as well as many methods for doing it - but this blog is not about either of those things. This blog is about the performance advantages of one particular [...]
Category: Parallel Programming
Tags: Intel Cilk Plus, Intel TBB, parallelism, performance, software development
Pipeline Speak, Part 2: The Second Part of the Sandy Bridge Pipeline
By Shannon Cepeda (Intel) (19 posts) on December 1, 2011 at 3:35 pm
Comments (0)
Last week I posted a blog explaining the front-end of the pipeline on Intel(R) Microarchitecture Codename Sandy Bridge. Today's blog completes the discussion of the pipeline by explaining the back-end, and then why it's helpful to know this stuff in general. The Back-End The back-end of the pipeline is responsible for executing the micro-operations the [...]
Category: Parallel Programming
Tags: "VTune Amplifier XE", Intel Microarchitecture Codename Sandy Bridge, performance analysis, software optimization
Pipeline Speak: Learning More About Intel® Microarchitecture Codename Sandy Bridge
By Shannon Cepeda (Intel) (19 posts) on November 22, 2011 at 3:17 pm
Comments (1)
As I'm sure you know, modern processors employ a technique called pipelining to increase instruction throughput. In a pipeline, various dedicated pieces of hardware on the processor each perform particular functions needed to process an instruction, on different instructions at the same time. For example, while one part of the pipeline is executing instruction A, [...]
Category: Parallel Programming, Uncategorized
Tags: Intel Microarchitecture Codename Sandy Bridge, Intel VTune Amplifier XE, performance tuning, software optimization
Celebrating at my final conference of 2011
By Shannon Cepeda (Intel) (19 posts) on November 14, 2011 at 8:58 am
Comments (0)
Getting to attend conferences to give training on Intel(R) Software Products is one of the perks of my job. And last week I got to exercise that perk when I had the opportunity to attend part of the Grace Hopper Celebration of Women in Computing conference. I presented a poster on our Intel® Parallel Studio [...]
Category: Parallel Programming
Tags: conference, Grace Hopper Celebration, Parallel Studio XE
Upcoming Webinars on Performance Tuning on Intel(R) Microarchitecture Codename Sandy Bridge
By Shannon Cepeda (Intel) (19 posts) on November 4, 2011 at 10:54 am
Comments (0)
I will be presenting a 2-part webinar on Nov 8th and 9th on performance tuning on Intel(R) Microarchitecture Codename Sandy Bridge. The webinars will walk through our Using Intel(R) VTune(TM) Amplifier XE on Sandy Bridge tuning guide. In each one I will walk through half of the guide, explaining the concepts and taking live questions. [...]
Category: Parallel Programming, Uncategorized
Tags: Intel(R) Microarchitecture Codename Sandy Bridge, Intel(R) VTune(TM) Amplifier XE, performance analysis, performance tuning, webinar
What we’ve been doing to make performance analysis easier on Intel® Microarchitecture Codename Sandy Bridge
By Shannon Cepeda (Intel) (19 posts) on June 27, 2011 at 9:33 am
Comments (0)
New Intel(R) Microarchitecture Codename Sandy Bridge support and tuning guide! We’ve been listening to your feedback on software tuning. Specifically, we’ve been working to make it even easier for developers to analyze software performance on Intel® Microarchitecture Codename Sandy Bridge. So now I’m really excited to tell you about the new Sandy Bridge: General Exploration [...]
Category: Performance and Optimization
Tags: Intel Microarchitecture Codename Sandy Bridge, Intel VTune Amplifier XE, performance analysis, performance tuning, Sandy Bridge
Parallelism Quick Quiz #3: Spot the fake parallelism law
By Shannon Cepeda (Intel) (19 posts) on June 28, 2010 at 7:34 am
Comments (2)
If you liked the last quick quiz, here's another: There are several guidelines to help developers or system tuners to predict the benefits of parallelism. Which of the ones below is a fake? A. Gustafson’s Law B. the Karp-Flatt metric C. Stevensen’s Corollary D. Amdahl’s Law In studying the theory of parallelism you would undoubtedly [...]
Category: Parallel Programming
Parallelism Quick Quiz #2: Which of these definitions is correct?
By Shannon Cepeda (Intel) (19 posts) on June 11, 2010 at 9:21 am
Comments (0)
If you liked the last quick quiz, here's another: The term is potential privacy infringement. Which of these definitions is correct? A. When a multi-threaded program has a security flaw in a web interface, potentially allowing access to the thread responding to web requests. B. When a thread accesses a variable created on the stack [...]
Category: Parallel Programming
Quick Quiz: Which of these parallelism technical terms did I just make up?
By Shannon Cepeda (Intel) (19 posts) on February 23, 2010 at 10:31 am
Comments (5)
A. agglomeration B. static partitioning C. livelock D. statistical exclusivity E. syncronization object If you haven’t given another thought to parallelism since your operating systems class in college, now’s the time to brush up. Intel and Programmer’s Paradise are hosting a technical roadshow right now to teach Windows C++ developers how to take advantage of [...]
Category: Events, Parallel Programming
Tags: Intel Parallel Studio, Parallelism Tech Days
What you Need to Know about Prefetching
By Shannon Cepeda (Intel) (19 posts) on August 24, 2009 at 10:34 am
Comments (0)
You may have heard that most current processors, including the Intel® Core™ i7 and Xeon® 5500 series, support prefetching. This blog will briefly cover the basics of what that means and how it affects your performance analysis. What is Prefetching? Prefetching in general means bringing data or instructions from memory into the cache before they [...]
Category: Uncategorized
Tags: Add new tag, Intel Core i7 processor, Intel Xeon(R) 5500 series, Nehalem, performance analysis, performance tuning, prefetch
Goldilocks and the Three Training Classes
By Shannon Cepeda (Intel) (19 posts) on July 6, 2009 at 9:12 am
Comments (0)
We have been working hard these past 3 months designing a new training class for C++ developers who want to learn parallelism. We’ve spent a lot of time contemplating what professional developers really need from their training. Some training classes assume too much, providing materials and samples on advanced topics without covering the basics. Some [...]
Category: Parallel Programming
Tags: C++, developer training, parallelism, training
Bay Area Developers - Attend pilot class of Intel's new Parallelism training FREE!
By Shannon Cepeda (Intel) (19 posts) on June 22, 2009 at 7:36 am
Comments (2)
For the past several months we have been hard at work on a new training class for developers. This class teaches the main concepts of threading and scalability to C++ developers new to parallelism. If this means you, and you work in the Bay area, join us for the pilot class, which will be free. [...]
Category: Parallel Programming
Tags: class, parallelism, training
Intel® Hyper-Threading Technology: Your Questions Answered
By Shannon Cepeda (Intel) (19 posts) on June 2, 2009 at 2:33 pm
Comments (5)
I have received a number of customer questions recently on Intel® Hyper-Threading Technology. Hyper-Threading Technology is available on the new Intel® Core™ i7 processor and the Xeon® 5500 series processors. Here are a few of my favorite questions and answers - ranging from the basics to more advanced topics. What is it? Intel® Hyper-Threading Technology [...]