So that is exactly what he set out to do.  Here is an article about the work that he has done. http://www.stolaf.edu/news/index.cfm?fuseaction=NewsDetails&id=4769  Professor Brown has started to do what I hope all of you will, which is to THINK PARALLEL, and better yet start to TEACH PARALLEL.  Together we can all figure out the best curriculums and the best ways to teach these new curriculums.

I encourage all of you to come to the Intel Academic Community often to see what your fellow academics are working on. Let us know what you are working on, and share some of your curriculum.

As I expected,  SC09 took most of Portland Expo floor space . Since I have my four-pages print out from SC Conference Activities, I was able to orient myself, and able to find Portland Ballroom for most of Paper and Technical sessions. Not surprisingly, I saw and heard a lot of voice and discussion in different languages, people with suit, tie and laptops. I was able to say hello and joined quite a discussions in Chinese, which is my first language, at exhibit hall, poster area and Ballroom. I  attended my first technical session ”Enabling Software Management for Multicore Caches with a Lightweight Hardware Support” presented by Jiang Lin, and Qingda Lu from Iowa and Ohio State Univ. about the management of shared caches in multi-core processors. In the article, a proposal of an affordable and lightweight hardware support to coordinate with OS-based cache management policies. The presenter concluded that the policies improve performance over LRU-based hardware cache management by 14.5% on 8-core systems. It was a good project.

Then I jumped into another ballroom in a less attended time for one of my interested, and bookmarked session on “On the Design of Scalable, Self-Configuring Virtual Networks” presented by David and Yonggang from Univ. of Florida on a novel Virtual Network design that supports dynamic, seamless addition of new resources with emphasis on scalability in a unified private IP address space. My interest attributed to the virtualization technology came from my group’s need to find an innovative way of supporting the parallel and multi-core programming education in academic classroom with realistic Hardware budget ( it is still the recession time for some of us right?). With our first parallelism integration with University of Southern California, providing maxima servers’ access for lab exercises with student/server ratio of more than 10 has to be done in an innovative way.

After two sessions, I also visited another interesting presentation: Space-Efficient Time-Series Call-Path Profiling of Parallel Applications presented by Zoltan etc. of Juelich Supercomputing Center. There is still one of my interested presentations that I could not make it on Thursday: Comparative Study of One-Sided Factorizations with Multiple Software Packages on Multi-Core Hardware  which will be presented by Emmanuel and Bilel etc of University of Tennessee, Knoxville).

Later, I went back to exhibit hall and started wandering through the most technology enriched IT professional/Server/laptop firm in the world. Passing through the amazing 1024 high definition movie streaming demo and almost zero latency 1024P Live broadcast from Tokyo Japan by Japan NTT, I came to a small booth, which has been my dream of “what I want to be  in future” kind of answer when I was a child: Institute of Computing Technology, Chinese Academy of Sciences, ICT is the cradle for China computer profession, having spun off new academic institutions and hi-tech companies(i.e. Lenovo) . Dawning 5000A Supercomputing System will be launched by this November, developed by ICT and Dawning Corp. under the support of Chinese Hi-tech Program, with 230 TFlops of peak performance and 160TFlops Linpack performance. All my following discussion at the booth is in Chinese.That seems to be the very productive time I spent, and the highlight of my experience at SC09.

About a hour later, I continued my brainstorming journey, paused at booths with brand names I saw everyday for some exhibit forum,  and ended at Microsoft boot for another long discussion ( stay tuned for my blog on it)

Starting today, developers can test the scaling of their applications to multi-core using the new Intel® Parallel Universe Portal, a cloud-based scaling analysis tool to help with parallel programming.  There is currently no charge for this service; it is available online here on the Intel Software Network at paralleluniverse.intel.com.

To read more of the story, see the article posted today.

]]> http://software.intel.com/en-us/blogs/2009/11/17/intel-parallel-universe-portal-a-new-cloud-based-analysis-tool-to-measure-multicore-application-scaling/feed/ http://software.intel.com/en-us/blogs/2009/11/05/teched-2009-europe/ http://software.intel.com/en-us/blogs/2009/11/05/teched-2009-europe/#comments Fri, 06 Nov 2009 01:05:03 +0000 Asaf Shelly http://software.intel.com/en-us/blogs/2009/11/05/teched-2009-europe/ Hi All,

If you are going to the event next week in Berlin then let me know about it. Maybe we can meet face to face and if there are enough of us perhaps even a gourp community meeting. This can be a good opportunity to meet the experts.

In any case, you are all welcome to join my session titled "Parallel Programming for Embedded". I will be presenting on Friday 10:45 - 12:00.

At the basis of this presentation is the fact that the hardware has always been parallel. This also caused the kernel drivers to live in a parallel environment, so even though embedded devices were late to adopt Multi-Core CPUs, the people who are working with the lower levels have always been working in parallel environments.

The session speaks of parallel systems in general side by side with embedded systems and infrastructure environemnts.

The goal of this session is to open the eyes and show the systems that have always been working in parallel and name the principles used with these systems.

You can read my previous blogs to learn more about this approach. For example these:

is dos the ideal parallel environment part iv

stateful programming a case study

Here are a few slides from this presentation.

Parallel Programming for Embedded TechEd 2009

USB Ping Pong

Hope to see you all there,
Asaf

The activities put students in the place of procesor cores and had them perform tasks in parallel. These activities proved to be popular among many of the students at the camp, however, some of the more advanced students did express that they felt the exercsies could seem childish.

My personal observation is that these exercises laid an excellent foundation that was built upon later with actual computer lab activites using OpenMP and Threading Building Blocks.

The activities are best done in groups of 4 or 5 individuals but even two in a single group can.

Without further ado - here is my promised write up:

Thinking Parallel

These role playing activities are designed to get you start thinking in parallel. They will also expose you to some terminology & concepts that we will use throughout the rest of the boot-camp. Many of these exercises were inspired from Chapter two if James Reinders’ book “Intel Threading Building Blocks”.

Objectives
The objectives for the following five exercises are to:
1) Explore domain & task decomposition using a mailer example.
2) Learn about race conditions and two ways to mitigate them.
3) Learn what a critical section does
4) How a reduction can eliminate a race condition.

Activity 1 – Explore Domain Decomposition

In this activity, each member of your team or group will play the role of a processor core, or more accurately, the role of a thread executing code on a core. Your team will explore how to use domain decomposition to accomplish the job of folding, stuffing, sealing, addressing, stamping & mailing multiple envelopes.

Time Required
fifteen minutes

Objective
Use scrap paper, some empty envelopes, and a pencil to explore the concept of parallelism
through domain decomposition.

Materials
1) 16 envelopes per table of 4 to 5 “processors”
2) 32 colored post-it notes (16 to represent stamps, 16 to represent address labels)
3) Pens or pencils

Setup
1) Divvy up the 16 envelopes & colored post-its so that each process gets a roughly equal share
2) Each “processor” (think student) must read over and become familiar with the “code” or instructions she is to execute so that the “code” is committed to memory.
Here is your “code” of instructions – For Domain decomposition – each processor does the same task but uses different data (represented here by different addresses)
a) Fold scrap paper
b) Stuff paper into envelop
c) Pretend to seal envelope (so we can re-use them later)
d) Address an “address label” and fix it to the middle of the envelope
You may use these fictitious addresses if you cannot come up with 16 of your own:

e) Fix another post-it (representing a stamp) to the stamp area of the envelope
f) Place envelope in table area designated “the mail box”

Monitor Time for completion of mailer exercise
1) Have someone on the team write down the time just prior to saying go
2) Each “processor” should complete his assigned set of envelopes as quickly as possible.
3) Record the time to complete the assigned mailer job. Time: _____________________
4) Record any observations about the nature of the tasks you do – which ones take longest, which one are fast? Were any processors idle for periods of time?

Activity 2 – Explore Task Decomposition

In this activity, your team will explore how to use a task decomposition to accomplish the job of folding, stuffing, sealing, addressing, stamping & mailing multiple envelopes.

Time Required
fifteen minutes

Objective
Use scrap paper, some empty envelopes, and a pencil to explore the concept of parallelism
through task decomposition.

Materials
1) 16 envelopes per table of 4 to 5 “processors”
2) 32 colored post-it notes (16 to represent stamps, 16 to represent address labels)
3) Pens or pencils

Setup
1) Divvy up the 16 envelopes & colored post-its so that each process gets a roughly equal share
a) Each “processor” will agree with team ahead of time which task or tasks he/she is committed
to accomplishing. Perhaps, one processor is assigned the tasks of Folding, Stuffing, Pretend
Sealing all the envelopes.
b) Another processor, or perhaps even two, are assigned the task of addressing the envelopes
Use same addresses as before
c) Another processor is assigned the role of stamping and mailing the envelopes

Monitor Time for completion of mailer exercise
1) Have someone on the team write down the time just prior to saying go
2) Each “processor” should complete his assigned tasks as quickly as possible.
3) Record the time to complete the assigned mailer job. Time: _____________________
4) Record any observations about the nature of the tasks you do – which ones take longest, which one are fast? Were any processors idle for periods of time?

Activity 3 –Vector Addition exposes race conditions

In this activity, your team will explore how to use a domain decomposition to accomplish the job of (mis)adding a set of numbers which we will call a vector. The activity exposes the problem that occurs when writes to a shared memory variable are not protected by a synchronization construct.

Time Required
fifteen minutes

Objective
Use some index cards, and pencils to explore the concept of a race condition.

Materials
1) 16 numbered index cards.
2) One index card labeled “Shared Sum”
3) 16 extra index cards are labeled “local memory”
4) Pencils

Setup
1) The 16 numbered index cards represent a vector of length 16 elements. These are divvied up roughly equally among all 4 to 5 “processors”
2) One extra index card is labeled “Shared Sum” and has the value 0 written on it and is placed in the middle of the table accessible to all processors
3) Several extra index cards are labeled “local memory” and are given to each processor as a scratch pad to add number on.

Execution
1) This is a domain decomposition exercise, where each processor “reads” the value of the “shared sum” and writes a new value to this shared sum – ignoring all the other processors previously written values – this is called a race condition.
Each processor should do these steps as quickly as possible:
a) “read” the value of the “shared sum” and writes that number on your own scratch pad.
b) add one of your “vector” card’s values to the sum on your scratch pad.
c) Immediately cross off the current value on the “shared sum” card and write your own value on the card (probably stomping over someone else’s value).
d) Repeat steps 5a – 5c until you are out of index cards
2) Compare the final value written on the “shared sum” with the known total (46)
3) Did your team compute the correct grand total for the vector sum?

Activity 4 –Vector Addition fixed with critical section

In this activity, your team will explore how a critical section can be used to guarantee that access to a shared memory region are protected – in other words, that writes to a shared variable are done in an orderly and synchronized fashion. It will also expose the performance penalty that can be taken as a result of critical sections.

Time Required
Fifteen minutes

Objective
Use some index cards, a magic marker & pencils to explore the concept of a critical section

Materials
1) 16 numbered index cards (we call it our vector)
2) 1 index card labeled “Shared Sum”
3) 16 extra index cards are labeled “local memory”
4) Magic marker
5) Pencils

Setup
1) The 16 numbered index cards represent a vector of length 16 elements. These are divvied up roughly equally among all 4 to 5 “processors”
2) One extra index cards labeled “Shared Sum” and has the value 0 written on it and is placed in the middle of the table accessible to all processors.
3) Several extra index cards are labeled “local memory” and are given to each processor as a scratch pad to add number on.
4) A Magic maker, known as “critical section”, is placed on the table next to the “shared sum”

Execution
1) We are now trying to synchronize access to shared memory by implementing a critical section. Our goal is to get rid of the race condition we encountered earlier.
2) New rule: “Each processor can only use the magic marker, named critical section, to write values to the “shared sum” index card. And – No processor can do any computations without first acquiring the magic marker, called critical section. As soon as a processor writes a new value to “shared sum” the processor should expeditiously return the capped critical section to the middle of the table”.
3) Each processor should do these steps as quickly as possible:
a) Acquire the critical section! If you failed to acquire the critical section you must wait for the marker to be placed back in the middle of the table.
b) Immediately cross off the current value on the “shared sum” card
c) Add the value of one of your index cards to the “shared sum” use a scratch pad if needed
d) Write the new value for sum on the globally shared “shared sum” card
e) Return the cap to the marker
f) Return the marker to the middle of the table
g) Repeat steps 5a(i) – 5a(v) until you are out of index cards
4) Compare the final value written on the “shared sum” with the known total (46)
5) Did your team compute the correct grand total for the vector sum?
6) What did you observe about how much time you spent idling versus time spent writing or calculating?

Activity 5 – Vector Addition fixed with reduction

In this activity, your team will explore how a reduction (or a partial sums approach) can be used to guarantee that access to a shared memory region are protected – in other words, that writes to a shared variable are done in an orderly and synchronized fashion. It will also demonstrate the benefit of replacing a critical section with a reduction wherever possible.

Time Required
Fifteen minutes

Objective
Use some index cards, & pencils to explore the concept of a critical section

Materials
1) 16 numbered index cards (we call it our vector)
2) 1 index card labeled “Shared Sum”
3) 4 index card labeled “Partial Sum”
4) 16 extra index cards are labeled “local memory”
5) Pencils

Setup
1) The 16 numbered index cards represent a vector of length 16 elements. These are divvied up roughly equally among all 4 to 5 “processors”
2) One extra index cards labeled “Shared Sum” and has the value 0 written on it and is placed in the middle of the table accessible to all processors.
3) The remaining “Partial sum” cards are divvied up among the processors
4) Several extra index cards are labeled “local memory” and are given to each processor as a scratch pad to add number on.

Execution
We are now trying to synchronize access to shared memory by implementing a reduction – which amounts to a collection of partial sums computed by each processor, followed by a grand total computed by a master thread. Our goal is to get rid of the race condition we encountered earlier, and do the parallel tasks in a more efficient manner.

Every processor will add up his/her own partial sum that represents the total of all the vector
elements assigned to him/her.

One processor will also be named to execute the “master thread” that adds up all the partial sum cards to create a grand total , that the master thread writes this grand total to the “shared sum” card.

1) Each processor should:
a) Add the values from all their assigned vector cards
b) Write the value to a “partial Sum” card
c) Give the “Partial Sum” card to the Processor who will execute the master thread
2) The Master Thread only should:
a) Compute his own partial sum
b) Wait for all other partial sums to arrive
c) Compute the grand total for all partial sums
d) Write the grand total on the “Shared Sum” card

3) Did your team compute the correct grand total for the vector sum?
What did you observe about how much time you spent idling versus time spent writing or calculating?

4) How effective was the reduction strategy at computing the sum in parallel versus the other methods tried?

Review Questions

Question 1: Describe a race condition
Question 2: What does a critical section do?

You are hereby invited to a gathering on November 17 at 5:30 pm in room C124 of the Oregon Convention Center in Portland. We are having a panel discussion focused on incorporating parallelism into the Computer Science curriculum. Of course, you might need to purchase a day pass to SC09 to attend, if you are not otherwise attending.

We generally all believe it is a good idea to weave parallelism throughout the CS curriculum. There are a variety of paths to get there, roughly corresponding to number of panelists, of which I will be the moderator and facilitator. The panel held last year at SC08, had a standing-room-only animated crowd. It happens to be available in 15 minute chunks: part 1, 2, 3, 4, 5, 6, and 7. I expect similar festivities this year.

Our distinguished panel is composed of

• Wen-mei Hwu, University of Illinois at Urbana-Champaign, who believes key computer architecture concepts, some performance optimization concepts, some program analysis concepts, some program transformation concepts, effective parallel programming patterns and algorithms, and fundamental parallelism concepts are required to train a successful undergraduate CS major.
• James Larus, Microsoft Research, who believes parallelism must be woven into the general series of courses, but sees the dilemma of the current awkward and crude tools imposing awareness of the underlying architecture on the student. He longs for a more elegant toolchain for use with students.
• Simon McIntosh-Smith, University of Bristol, who has succumbed to the "Snow White" syndrome of advocating the dwarves parallel patterns from UCB. He also sees the utility of teaching the current prevalent tools: MPI and OpenMP, while remaining sensitive to the emerging potential standards: CUDA, OpenCL, Ct, map-reduce, etc.
• Bob Chesebrough, Intel, who sees the trouble in River City of a late introduction of parallelism to students, and of course recommends the "Think Method", in this case the "Think Parallel" method. Parallelism is all around and the key concepts can be conveyed without a computer.
• Steve Parker, nVidia, who believes and has done many things. There needs to be a teaser to get you to come to the event. This is it.
• Charlie Peck, Earlham College, who sees faculty education as key activity to get right, since many CS faculty have limited first hand experience with the myriad faces of parallelism. Involving students is a key part of this, for a unique form of learning takes place via an apprenticeship model of student involvement.

For several years now, we have been a parallel education working group composed of broad representation from industry, colleges/universities, hardware manufactures, and labs We are about to call ourselves something like "The Educational Alliance for a Parallel Future." I now know first hand what is involved in morphing from a working group to an alliance. When you are getting ready to make a tee-shirt, alliance ends up sounding sounding way cooler, and actually better reflects who we are. We will also be releasing a parallel crossword puzzle. This is not one solved in parallel, though it might be if someone is looking over your shoulder. The subject matter is of many things parallel. Stay tuned, we'll point you to it, once it debuts at SC09.

Dear Colleagues,

As a member of the Informatics Education Europe Organizing Committee it is a pleasure for me to inform you of the IEE IV 2009 conference which will take place on November 5-6 in Freiburg, Germany.

Informatics Education Europe IV is the fourth in a series of conferences promoted by ACM to provide a forum for European Informatics academics to discuss the latest developments in the teaching and learning of Informatics in Europe. The conference is not exclusive, experts in any area within the spectrum of Informatics are welcome and, while the focus is on Europe, academics from elsewhere in the world are also invited to participate.

We have set up a very interesting programme ranging from topics like "Teaching programming" to "International cooperation" and we are also proud to announce our invited speakers: Hans-Ulrich Heiss from the TU Berlin with his talk about "Accreditation of Informatics Degree Programs in Europe: Straitjacket or Cloak?" and Mark Guzdial from Georgia Institute of Technology with his talk "Meeting Everyone's Need for Computing".

Further information on the conference can be found at the website.

I welcome you to forward this information to all your colleagues who might be interested in the conference.

regards
Christoph Hermann

University of Freiburg

I gave my Computer Architecture midterm yesterday. One of the four problems was to predict the output of a 17 byte program. This is with an assembly language where the bulk of the instructions are three bytes. The correct answer is of course 42, once the unconditional branch is successfully mutated to an untaken conditional branch.

•  
  •  
    •  
      C1 00 07 1C E1 00 07 04 00 0E 38 00 2A 00 41 00 0A

•  
  •  
    •  
      lda adj,d
asla
sta adj,d
br skip
adj: .equate 7
msg: .ascii "8\x00*\x00"
skip: stro msg,d
.end

Only 20% of the class got it right, even though I told them days before they would. By the end of the semester they will be more adept. Earlier, I'd given them the project of writing a solution to the Tower of Hanoi problem in assembly language. A student challenged me to write it in under 100 bytes. My current version is 76 bytes and I see how to prune it down to 71 bytes.

The most bloated document editor on my computer is expressed in 27.6 megabytes, and while it is doing a lot more than the Tower of Hanoi problem, it is certainly not doing six orders of magnitude more work. Am I sniping my students by introducing them to arcane dark arts?

We are fast approaching a time when single CPU personal computers will be about as prevalent as clocks with mechanical hands. We can program parallel architectures with mechanical hands, but they may not perform as fast as we want them to.

Advocating "Teach Parallel" makes a lot sense. It may make make equal sense to "Teach Performance" as well. For at least the time being, they might just go hand in hand, quietly humming "Till There Was You".

On Oct.21st till Oct.23rd, a faculty workshop on curriculum of Embedded was held at Zhejiang University, China. The workshop witnessed the kick-off of the Intel Higher Ed. Atom based "Embedded" university program. Plagues of Intel-university joint labs of Embedded Technology were delivered to faculty attendees from 26 universities that receive Intel donated Atom platforms. With regards to the current mainstream product lines, two types of Atom platforms with N series and Z series processors were chosen for the joint labs equipments. In addition to the content Intel provides on Atom architecture, Moblin and software tools, for the first time, we invited partners - platform vendors to deliver their training on the provided platforms and the labs they recommend for curricula.

After the two days training for the platforms, faculty attendees were getting to the point of what content and how to adopt Atom to the curricula, which led to a hot discussion on the last day open forum. For those who are teaching classes on application development, they'd like to know the "new story" Intel would tell for Atom, comparing to its current industry rivals. For those "hardcore embedded" faculty, they are interested in how to get needed materials for board design (e.g., processor power module reference design), probing the processor information through JTAG, bootup/BIOS (or BSP as current term for embedded) procedures to program the IOs etc. Though shared with the corresponding online resources (EDC, the Software Developers Manuals), faculty still feel it a bandwidth consuming job to convert them to teachable tutorials that can be used at campus.

Though there is still work to do, the good news is that our university fellow travelers are warmed up and have shown interests in collaborating with us to create whatever is missing but crucial to adopt Atom in the curricula. And that makes this reloaded initiative a blessed one.

Half way through the second day we ran into a minor problem with one of the lab exercises that is supposed to demonstrate load imbalance. We had accidently installed the solution file in place of the problem code on the participant’s machines. After giving them a few minutes to play with the lab exercise, I attempted to “demonstrate” the problem to the class using Intel’s Parallel Amplifier. To my surprise there was no evidence of a problem at all. While I was busily checking the project settings to make sure the tool was gathering data correctly, it became clear to me just how smart these folks really are. One of the “students” interrupted me to suggest how removing the OpenMP schedule clause in the code would cause an interesting load imbalance and make for a more interesting lab exercise. All the while he was explaining it, the rest of the participants were grinning and nodding in agreement. Rather than an embarrassing mistake on our part, I should have sold it as a “curriculum development” exercise.

The purpose of this event was to review our course materials with the faculty so they could “scale out” the training to other universities in Romania. From what I saw last week, I’d say these folks are ready to take this show on the road.

If you have tracked this for a while, you find that there is always a set of articles about higher education right around this time of year in the press -- I think it's a matter of those mid-career journalists reacting to their 1st -> nth child going off the college each August/September.  Or their reaction to writing the tuition check.  This year, the buzz has been very heavy over the use of online tools.  Even here inside Georgia Tech there's been an interesting tit-for-tat argument among professors, each side citing studies on whether video lectures, blogs, tweets, etc. enhance or distract from the learning process.

On the one side -- yes, there is a revolution in content delivery that is on-going, and higher education will have to react.  And there is good evidence that ignoring this makes for poorer student results as well as being a poor pedagogical (and economic) choice.  Some studies have even shown that using social media (in a very broad definition) can have a strong positive impact.  This is what journalists tend to pick up on -- after all, if you can just put your kids in front of youtube and get them a university education, isn't that a much better choice?  (For your pocket books at least...)

The other side fires back with their own studies, though, and those tend not to get heard as much.  There's evidence, they say (and I'm just passing this along, since I haven't done any demographic studies myself), that the higher student grades tend to be because the retention rates in the heavily web-driven courses drops way down.  Students who would get A's if you just stood up front and hummed the theme to "Shaft" all day will stick it out, but the students that really need the benefit of the full educational experience walk away unsatisfied, thereby raising the average grades.  So, the traditionalists argue, the whole things should be ignored.

As with many things in life, I think that the truth lies somewhere in the middle.  I was involved with an experiment with full online lectures, online daily quizzes, coupled with small weekly recitation sessions back over 10 years ago.  Much has changed in the interim, but I think some of the core observations are the same -- students really liked having the resources available, but they procrastinate unless they have a driver function like "show up at 12:00 on Mondays, Wednesdays, and Fridays".  The online quizzes were nice because they could be that forcing function.  But the lectures tended to be a mess -- students wouldn't keep up, and so the servers would get completely slammed by them trying to watch 3 weeks of lectures in the 24 hours before the next test.  And, of course, students just could parse that much material in such a short time, so their grades and long-term retention of information suffered.

So anyone have any thoughts?  Are brick-and-mortar universities doomed?  Or, more importantly, are they missing out on something they *could* be doing for their students and alumni?

We're right in the middle of talking about synchronization and how you go about building semaphores or mutexes at the kernel level, so it's pretty natural that we talk about parallelism in pretty much every lecture at the moment.  But it's amazing how many times it comes up even when you aren't dealing with explicitly parallel topics -- library design, memory management, file systems.  Not to mention the interesting issues that shared vs partitioned L3 caches, NUMA, and other multicore-related architecture trends cause for scheduling algorithms, paging table management, etc.

For those of you who are just starting down the road of adding parallelism, I have a very simple suggestion that I like doing at least once a week (in some guise or another).  Just stop somewhere in your lecture, look out at the class, and ask "Do you think this will still make sense in two years?  Will the next-next generation of multicore chips still do things this way?"  Sometimes the answer's yes, sometimes it's no... but the discussion is almost always interesting.

I'll try to lay out some of the specific things I've done in my class in subsequent entries -- little modules and small self-contained units that try to weave multicore/parallel topics into the curriculum in bite-sized chunks.  Questions, suggestions, and contributions are very welcome!

12/3 | 4PM | 2405 Siebel Center for Computer Science

UPCRC Illinois Research Seminar: A Structured, Unified Approach to Multi-Core and Many-Core Computing - with Applications by Michael McCool, Intel & U of Waterloo

What are the pro and cons of Moodle for corporate use? What changes are needed to make Moodle better for corporate use? A lot of similar questions like these have been asked on Moodle.org and Moodle community. Now let me give my two cents to those questions.

In my first blog, I mentioned Moodle's Philosophy of learning (http://docs.moodle.org/en/Philosophy) which is focuses on collaboration, activities and critical reflection. This social-constructive approach involves a strong community of learning orientation rather than simply computing courses and exercises online. Those are right, we want collaboration, activities and critical reflection, but in our case, the first difference comes in that we are requesting collaboration and social- constructive approach at a very earlier stage, that is at the time of creating courseware (either traditional instructor-lead or online virtual class) rather than the time that these courses are delivered on Moodle platform.

Why it happens in our case, the answer is straight forward. No courses have been created yet. There is a growing gap between academic and Industry world recently on computer science education, especially in last three years. Currently, parallel computing has become widely used in all works of life. As a result, more pertinent applications are needed to fully using the high performance of its multi-core processors. Major chip companies have successfully launched a variety of dual-core and Quad-core processor systems. However, technology advanced so fast that most academic institutions haven’t yet able to catch up and add the multi-core and parallel programming into their CS curriculum.

How to educate more software engineers who know how to fully utilize the performance advantage of multi-core processor has become a key challenge for Computer science education. There are the needs for more of a community approach to driving curriculum changes where the teacher and learner from academic side, and corporation, government and researcher from other sides all collaborate in its development. That is the major force and need that an industry like us wants a learning management system (LMS) that can provide technology and a platform of collaboration for academic community to facilitate the integration of multi-core and parallelism education into university curriculum. As a Moodler, we all know that a constructive amount of connected activities within a learning community is a very powerful stimulant for learning, not only bringing people closer together but promoting synergy among educators and learners.

After the 6 months of work on Moodle, it seems to me that the advantages of Moodle is not its no-cost open source application nature, but more about the flexibility of the application as open-source to be adapted to our corporation’s specific needs. That's one of the great things about Moodle and open source; you can make it do whatever you require.

By viewing our moodle site, you will find out that, at this time, it does not look like that the social-constructive constituents, a great advantage of Moodle, have been enabled. Yes, you are right, and got it. However, we have laid a very strong foundation , a capability of supporting more active collaboration coming in our way, which is Moodle itself. Apparently some customization has been done (and more coming shortly) for our processes which are not required on the academic side. There are a few major areas that are currently still under development. Some of them we haven’t yet find solution:
1. Collaboration on course creation
2. Flexibility of course metadata management
3. Course submission process
4. Course creation scheduling
5. Peer review and comment
6. Course editing and approval process
7. Course life span management and version control
I will give my two cents on those topics whenever it becomes available.

Still, CS continues to have ‘a bad rep’ or at least computer scientists continue to think of themselves as ‘second-class scientists’. Some in the field believe there will be no successful interactions with other colleagues and scientists until CS is positioned as as much of a science as others and this implies uniting the community and presenting a coherent interface to the rest of the world. Finally, as Wendy Hall’s closing remarks pointed, it also implies defining when a new discipline begins and when we are simply mixing together 1 or 2 disciplines to solve various aspects of a problem. If a multidisciplinary collaboration is to be fruitful, it has to be taken at the educational level and given a long-term commitment. Words widely repeated during the conference even when referring to multi-disciplinary research.

Whilst aware of the need to work collaboratively; many computer scientists are afraid that this will distil the importance and identity of their already misrepresented field. What do you believe will happen when mixing CS with other disciplines?