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Posts in the "Performance and Optimization" Category 
What is Intel(r) Secure Key Technology?
By Gael Holmes Hofemeier (Intel) (132 posts) on May 14, 2012 at 4:15 pm
Comments (0)
In a nutshell: Intel® Secure Key, was previously code-named Bull Mountain Technology. It is the Intel name for the Intel® 64 and IA-32 Architectures instruction RDRAND and its underlying Digital Random Number Generator (DRNG) hardware implementation. Among other things, the DRNG using the RDRAND instruction is useful for generating high-quality keys for cryptographic protocols. Because [...]
Category: Intel SW Partner Program, Manageability & Security, Performance and Optimization, Ultrabook
Tags: Bull Mountain, Digital Random Number Generator, DRNG, Intel Secure Key, rdrand
TACC symposium and programming two SMP-on-a-chip devices
By James Reinders (Intel) (48 posts) on April 26, 2012 at 8:28 pm
Comments (0)
one presenter exclaimed “Time spent optimizing for MIC is time well spent because it optimizes your code for non-MIC processors at the same time.”
Category: Parallel Programming, Performance and Optimization, Software Tools
Tags: Cilk Plus, Intel MIC, Knights Corner, Knights Ferry, many-core, multi-core, parallel programming, parallelism, SCC
Intel Announces the New Intel® SDK for OpenCL* Applications 2012
By Arnon Peleg (Intel) (5 posts) on April 25, 2012 at 3:38 am
Comments (6)
In support of the recent announcement of the 3rd Generation Intel® Core™ Processors, Intel has released the Intel® SDK for OpenCL* Applications 2012. For the first time, OpenCL* developers using Intel® architecture can utilize compute resources across both Intel® Processors and Intel® HD Graphics Driver 4000/2500
Category: Academic, Game Development, Graphics & Media, Parallel Programming, Performance and Optimization, Server, Software Tools
Tags: "Intel OpenCL SDK", "Intel OpenCL", openCL, vcsource_product_oclsdk, vcsource_type_event, vcsource_type_news
SIMD tuning with ASM pt. 1 - Stars & Constellations
By Matt Walsh (Intel) (1 posts) on April 24, 2012 at 3:19 pm
Comments (2)
ASM? You mean assembly language? I haven't looked at that since my senior project! How arcane! And compilers are so smart anymore, why should I care? I used to feel the same way...albeit with a latent desire to learn it as I wish I knew Latin. Then one day I found myself out of options [...]
Category: Performance and Optimization
Tags: assembly, Intel(R) Performance Tuning Utility, Intel® Streaming SIMD Extensions 4, SSE
History of … one CPU instructions: Part 1. LDDQU/movdqu explained
By Maxym Dmytrychenko (Intel) (1 posts) on April 16, 2012 at 1:48 am
Comments (2)
Once upon the time and back to 2000, Intel brought to market NetBurst microarchitecture (http://en.wikipedia.org/wiki/NetBurst_%28microarchitecture%29 ) with Pentium 4 CPUs . At 2004, with its Prescott revision/core and as a part of SSE3 instruction set, we’ve got LDDQU instruction, Where the main focus area used to be - Video Encoding: The most compute-intensive part of [...]
Category: Performance and Optimization, Ultrabook
Tags: assembler, CPU, instruction
My wife bought an Ultrabook – and LOVES it!
By Matt Ployhar (Intel) (46 posts) on April 2, 2012 at 9:17 pm
Comments (0)
Right now we have 4 PC laptops in our house; 5 if you count the iPad 2 being a ‘personal computing’ device. There’s my work HP Pavilion dv6, my personal Alienware M11x, her former Dell XPS M1530, which just got replaced by the Asus Zen book UX 31. In my sixteen years of being in [...]
Category: Academic, Events, Game Development, Graphics & Media, Intel SW Partner Program, Intel® AppUp Developer Program, Mobility, Performance and Optimization, Power Efficiency, Ultrabook, Uncategorized
Tags: PC Gaming Ultrabook, Ultrabook
Dualbooting Windows 7 and Windows 8
By Rami Radi (Intel) (1 posts) on March 20, 2012 at 2:08 pm
Comments (5)
The Windows 8 Consumer Preview ISO image became public a few days ago, which is available here, so I am sure a lot of people are interested in trying it out on their development systems without replacing their current Windows 7 installation. If you've ever dual booted a system before, the procedure for doing it [...]
Category: Academic, Intel SW Partner Program, Parallel Programming, Performance and Optimization, Power Efficiency, Site News & Announcements, Software Tools, Uncategorized
Tags: dual boot, dual booting, dualboot, Windows 8, Windows 8 Consumer Preview
Ultrabooks are here and so is our new community!
By Jeffrey Rott (Intel) (22 posts) on December 31, 2011 at 8:33 am
Comments (2)
Without a doubt, one of the most exciting developments in the tech world for 2011 was the introduction of the Ultrabook. We put a reference design out there and OEMs took it and ran with it. Most of the models that arrived were slim, sleek, powerful and yet power-efficient. I brought one of the current [...]
Category: Graphics & Media, Performance and Optimization, Power Efficiency
Tags: Ultrabook
Register for Intel(R) Technical Presentation "Analysis of hybrid applications with the Intel(R) Cluster Studio XE 2012"
By RAVI (Intel) (18 posts) on December 2, 2011 at 10:31 am
Comments (3)
Gergana Slavova, Technical Consulting Engineer, will be presenting "Analysis of hybrid applications with the Intel(R) Cluster Studio XE 2012" on Dec 7th at 9am PDT. Please register!
Category: Academic, Embedded Computing, Game Development, Graphics & Media, Open Source, Parallel Programming, Performance and Optimization, Software Tools, Uncategorized
Paving the Road to OpenMP 4
By Michael Klemm (Intel) (5 posts) on November 21, 2011 at 7:16 am
Comments (0)
The dust of SC’11 starts to settle and several announcements around OpenMP have been made in Seattle. There has been a change in the OpenMP Architecture Review Board and Language Committee. Several new members have joined the committee and started to actively participate in the development of future OpenMP versions. Also, Michael Wong (IBM) has [...]
Category: Parallel Programming, Performance and Optimization, Software Tools
MIC architecture support by software tools - SC11 wrap-up
By James Reinders (Intel) (48 posts) on November 17, 2011 at 4:24 pm
Comments (1)
This week we demonstrated the Knights Corner co-processor at SC11 and we had many developers demonstrating real results with the prototype systems. During the "SC11 season," a number of tool vendors announced they will be providing versions of their software tailored to supporting MIC architecture, starting with the Knights Corner co-processor. Here are the ones I know [...]
Category: Parallel Programming, Performance and Optimization, Server
Tags: Knights Corner, Knights Ferry, MIC
quick chat about MIC architecture with Mike Dewar, NAG
By James Reinders (Intel) (48 posts) on November 17, 2011 at 3:37 pm
Comments (3)
I ran into Mike Dewar at SC11 today as the exhibition draws to a close. Mike is the CTO of NAG Ltd. - a company we've had the good fortune to work with for years. NAG is one of a handful of companies that have been providing feedback on our Knights Ferry (prototype MIC architecture). [...]
Category: Parallel Programming, Performance and Optimization, Server, Software Tools
Tags: MIC, NAG
Seeing One TeraFlop/sec, the software side, and feeling a bit emotional
By James Reinders (Intel) (48 posts) on November 17, 2011 at 9:27 am
Comments (0)
I've known this day was coming - but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) per second - I was surprised by my emotional reaction inside. Hard to describe; it was a good feeling. Tuesday November 15, 2011, we showed a Knights Corner co-processor for the first time [...]
Category: Parallel Programming, Performance and Optimization, Software Tools
Tags: Knights, Knights Corner, MIC, MKL
Open Parallel: Optimizing Web Performance with TBB
By Nicolas Erdody (1 posts) on November 16, 2011 at 2:39 pm
Comments (1)
Open Parallel is a research and development company that focuses on parallel programming and multicore development. We are a bunch of highly skilled geeks from various backgrounds that work together on problems in parallel programming and software development for multicore and manycore platforms. At LinuxConf (LCA2010) James Reinders gave a talk about the Threading Building [...]
Category: Open Source, Parallel Programming, Performance and Optimization, Power Efficiency, Software Tools
Tags: HipHop, Intel Software Partner Program, James Reinders, multi-core, Open Source, parallel programming, parallelism, Perl, PHP, TBB
AES Counter Mode details (Intel AES-NI implementation)
By Nicolae Popovici (Intel) (1 posts) on November 11, 2011 at 8:29 am
Comments (0)
In this article we’ll take a closer look at AES counter (CTR) mode implementation from Intel® AES-NI library (it can be downloaded from http://software.intel.com/en-us/articles/download-the-intel-aesni-sample-library/). AES stands for Advanced Encryption Standard and it is a symmetric encryption standard. More detailed information about AES at http://de.wikipedia.org/wiki/Advanced_Encryption_Standard. AES-NI refers to Intel® Advanced Encryption Standard (AES) Instructions Set which [...]