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<channel>
	<title>Intel Software Network Blogs &#187; Software Engineering</title>
	<atom:link href="http://software.intel.com/en-us/blogs/category/software-engineering/feed/" rel="self" type="application/rss+xml" />
	<link>http://software.intel.com/en-us/blogs</link>
	<description></description>
	<pubDate>Fri, 06 Nov 2009 23:30:30 +0000</pubDate>
	<generator>http://wordpress.org/?v=2.6.5</generator>
	<language>en</language>
			<item>
		<title>TechEd 2009 Europe</title>
		<link>http://software.intel.com/en-us/blogs/2009/11/05/teched-2009-europe/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/11/05/teched-2009-europe/#comments</comments>
		<pubDate>Fri, 06 Nov 2009 01:05:03 +0000</pubDate>
		<dc:creator>Asaf Shelly</dc:creator>
		
		<category><![CDATA[Academic]]></category>

		<category><![CDATA[Events]]></category>

		<category><![CDATA[Intel® Software Network 2.0]]></category>

		<category><![CDATA[Mobility]]></category>

		<category><![CDATA[Parallel Prog. &amp; Multi-Core]]></category>

		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[guest blogger]]></category>

		<category><![CDATA[TechEd]]></category>

		<category><![CDATA[www.AsyncOp.com]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/11/05/teched-2009-europe/</guid>
		<description><![CDATA[Hi All,
If you are going to the event next week in Berlin then let me know about it. Maybe we can meet face to face and if there are enough of us perhaps even a gourp community meeting. This can be a good opportunity to meet the experts.
In any case, you are all welcome to [...]]]></description>
			<content:encoded><![CDATA[<p>Hi All,</p>
<p>If you are going to the event next week in Berlin then let me know about it. Maybe we can meet face to face and if there are enough of us perhaps even a gourp community meeting. This can be a good opportunity to meet the experts.</p>
<p>In any case, you are all welcome to join my session titled "Parallel Programming for Embedded". I will be presenting on Friday 10:45 - 12:00.</p>
<p>At the basis of this presentation is the fact that the hardware has always been parallel. This also caused the kernel drivers to live in a parallel environment, so even though embedded devices were late to adopt Multi-Core CPUs, the people who are working with the lower levels have always been working in parallel environments.</p>
<p>The session speaks of parallel systems in general side by side with embedded systems and infrastructure environemnts.</p>
<p>The goal of this session is to open the eyes and show the systems that have always been working in parallel and name the principles used with these systems.</p>
<p>You can read my previous blogs to learn more about this approach. For example these:</p>
<p><a href="http://software.intel.com/en-us/blogs/2008/10/29/is-dos-the-ideal-parallel-environment-part-iv/">is dos the ideal parallel environment part iv</a></p>
<p><a href="http://software.intel.com/en-us/blogs/2009/07/27/stateful-programming-a-case-study/">stateful programming a case study</a></p>
<p>Here are a few slides from this presentation.</p>
<div id="attachment_11631" class="wp-caption alignnone" style="width: 310px"><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/11/parallel-programming-for-embedded-slide-2.jpg"><img class="size-medium wp-image-11631" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/11/parallel-programming-for-embedded-slide-2-300x225.jpg" alt="Parallel Programming for Embedded TechEd 2009" width="300" height="225" /></a><p class="wp-caption-text">Parallel Programming for Embedded TechEd 2009</p></div>
<div id="attachment_11632" class="wp-caption alignnone" style="width: 310px"><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/11/parallel-programming-for-embedded-slide-56.jpg"><img class="size-medium wp-image-11632" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/11/parallel-programming-for-embedded-slide-56-300x225.jpg" alt="USB Ping Pong" width="300" height="225" /></a><p class="wp-caption-text">USB Ping Pong</p></div>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/11/parallel-programming-for-embedded-slide-71.jpg"><img class="alignnone size-medium wp-image-11634" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/11/parallel-programming-for-embedded-slide-71-300x225.jpg" alt="" width="300" height="225" /></a></p>
<p>Hope to see you all there,<br />
Asaf</p>
]]></content:encoded>
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		</item>
		<item>
		<title>Change of type alignment and the consequences</title>
		<link>http://software.intel.com/en-us/blogs/2009/11/05/change-of-type-alignment-and-the-consequences/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/11/05/change-of-type-alignment-and-the-consequences/#comments</comments>
		<pubDate>Thu, 05 Nov 2009 22:56:36 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[64-bit]]></category>

		<category><![CDATA[64-bit Coding]]></category>

		<category><![CDATA[C++]]></category>

		<category><![CDATA[Data Alignment]]></category>

		<category><![CDATA[Viva64]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/11/05/change-of-type-alignment-and-the-consequences/</guid>
		<description><![CDATA[When porting software one of the task a developer faces is to change types' sizes and rules of their alignments. Not so long ago we provided support of the diagnosing rule allowing you to detect data structures which use memory on 64-bit inefficiently in Viva64 analyzer. But there is still some research work to be [...]]]></description>
			<content:encoded><![CDATA[<p>When porting software one of the task a developer faces is to change types' sizes and rules of their alignments. Not so long ago we provided support of the diagnosing rule allowing you to detect data structures which use memory on <a href="http://viva64.com/terminology/64-bit.html">64-bit</a> inefficiently in <a href="http://viva64.com/terminology/Viva64.html">Viva64</a> analyzer. But there is still some research work to be carried out in this field and I look through the messages concerning this topic in forums with attention.</p>
<p>This time my attention was attracted by a message in RSDN "<a href="http://www.viva64.com/go.php?url=218">Alignment on 64-bit architectures</a>" running as follows:</p>
<p><i>Today I have faced a problem in Linux. There is a data structure consisting of several fields: 64-bit double, 8 unsigned char and one 32-bit int. Altogether it is 20 bytes (8 + 8*1 + 4). On 32-bit systems sizeof is 20 bytes and everything is OK. But on the 64-bit Linux sizeof returns 24 bytes. That is, an alignment at the 64-bit border takes place.</i></p>
<p>After that the author dwells upon data compatibility and asks for advice how to pack data in the structure. But at the moment we are not interested in this. What we are interested in is that there is a new type of errors which can occur when porting applications on a 64-bit system.</p>
<p>It is clear and common that when sizes of fields in a structure change, the size of the structure itself changes too because of this. But this is a different case. The size of the fields remains the same but the size of the structure will change too due to different <a href="http://viva64.com/terminology/Data_alignment.html">alignment</a> rules. This behavior can lead to various errors, for example, incompatibility of the formats of the data being saved.</p>
<p>Linux systems are not supported by Viva64 yet, but I decided to find out if such an error can occur in Windows systems. For this purpose I took an example of the code printing types' sizes and alignment from the article "<a href="http://www.viva64.com/go.php?url=219">C++ data alignment and portability</a>". I've modified it a bit for Visual Studio and got this program:</p>
<pre>#include &lt;iostream&gt;
using namespace std;

template &lt;typename T&gt;
void print (char const* name)
{
  cerr &lt;&lt; name
       &lt;&lt; " sizeof = " &lt;&lt; sizeof (T)
       &lt;&lt; " alignof = " &lt;&lt; __alignof (T)
       &lt;&lt; endl;
}

int _tmain(int, _TCHAR *[])
{
  print&lt;bool&gt;        ("bool          ");
  print&lt;wchar_t&gt;     ("wchar_t       ");
  print&lt;short&gt;       ("short int     ");
  print&lt;int&gt;         ("int           ");
  print&lt;long&gt;        ("long int      ");
  print&lt;long long&gt;   ("long long int ");
  print&lt;float&gt;       ("float         ");
  print&lt;double&gt;      ("double        ");
  print&lt;long double&gt; ("long double   ");
  print&lt;void*&gt;       ("void*         ");
}
</pre>
<p>I compared the data I'd got with the data described in the article "C++ data alignment and portability" for GNU/Linux systems and now give them in Table 1.</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/blog-aligment.png"><img src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/blog-aligment-246x300.png" alt="" width="246" height="300" class="alignnone size-medium wp-image-10977" /></a><br />
Table 1. Types' sizes and alignment.</p>
<p>Let's study this table. Pay attention to the marked cells relating to long int and double. These types' sizes don't depend on the architecture's size and therefore don't change. Both on 32-bit and 64-bit systems their size is 8 byte. But alignment is different for 32-bit and 64-bit systems. It can cause change of the structure's size. When we implement Viva64 for Linux we'll take into consideration the possible errors relating to this.</p>
<p>In Windows systems, there are no such problems with alignment change. Pay attention that alignment of all the types doesn't change or changes together with the type's size. That is good - Windows developers have one potential problem off.</p>
]]></content:encoded>
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		</item>
		<item>
		<title>In the company of friends</title>
		<link>http://software.intel.com/en-us/blogs/2009/11/04/in-the-company-of-friends/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/11/04/in-the-company-of-friends/#comments</comments>
		<pubDate>Wed, 04 Nov 2009 20:57:19 +0000</pubDate>
		<dc:creator>wolfmurphy</dc:creator>
		
		<category><![CDATA[Academic]]></category>

		<category><![CDATA[Parallel Prog. &amp; Multi-Core]]></category>

		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[panel discussion]]></category>

		<category><![CDATA[SC09]]></category>

		<category><![CDATA[tee shirts]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/11/04/in-the-company-of-friends/</guid>
		<description><![CDATA[




You are hereby invited to a gathering on November 17 at 5:30 pm in room C124 of the Oregon Convention Center in Portland. We are having a panel discussion focused on incorporating parallelism into the Computer Science curriculum. Of course, you might need to purchase a day pass to SC09 to attend, if you are [...]]]></description>
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<p><body><br />
You are hereby invited to a gathering on November 17 at 5:30 pm in room C124<img src="http://software.intel.com/file/23528" alt="room circled on floorplan" /> of the Oregon Convention Center in Portland. We are having a panel discussion focused on incorporating parallelism into the Computer Science curriculum. Of course, you might need to purchase a day pass to <a href="http://sc09.supercomputing.org/">SC09</a> to attend, if you are not otherwise attending.</p>
<p>We generally all believe it is a good idea to weave parallelism throughout the CS curriculum. There are a variety of paths to get there, roughly corresponding to number of panelists, of which I will be the moderator and facilitator. The panel held last year at SC08, had a standing-room-only animated crowd. It happens to be available in 15 minute chunks: part <a href="http://software.intel.com/en-us/videos/stop-teaching-sequential-programming-forum-at-super-computing-08-education-forum-pt1/">1</a>, <a href="http://software.intel.com/en-us/videos/sequential-programming-is-no-more-why-are-we-still-teaching-it-panel-super-computing-08-education-forum-pt2/">2</a>, <a href="http://software.intel.com/en-us/videos/sequential-programming-is-no-more-why-are-we-still-teaching-it-panel-super-computing-08-education-forum-pt3/">3</a>, <a href="http://software.intel.com/en-us/videos/sequential-programming-is-no-more-why-are-we-still-teaching-it-panel-super-computing-08-education-forum-pt4/">4</a>, <a href="http://software.intel.com/en-us/videos/sequential-programming-is-no-more-why-are-we-still-teaching-it-panel-super-computing-08-education-forum-pt5/">5</a>, <a href="http://software.intel.com/en-us/videos/sequential-programming-is-no-more-why-are-we-still-teaching-it-panel-super-computing-08-education-forum-pt6/">6</a>, and <a href="http://software.intel.com/en-us/videos/sequential-programming-is-no-more-why-are-we-still-teaching-it-panel-super-computing-08-education-forum-pt7/">7</a>. I expect similar festivities this year.</p>
<p>Our distinguished panel is composed of</p>
<ul>
<li><strong>Wen-mei Hwu</strong>, University of Illinois at Urbana-Champaign, who believes key computer architecture concepts, some performance optimization concepts, some program analysis concepts, some program transformation concepts, effective parallel programming patterns and algorithms, and fundamental parallelism concepts are required to train a successful undergraduate CS major.
</li>
</p>
<li> <strong>James Larus</strong>, Microsoft Research, who believes parallelism must be woven into the general series of courses, but sees the dilemma of the current awkward and crude tools imposing awareness of the underlying architecture on the student. He longs for a more elegant toolchain for use with students.
</li>
</p>
<li>
<strong>Simon McIntosh-Smith</strong>, University of Bristol, who has succumbed to the "Snow White" syndrome of advocating the dwarves parallel patterns from UCB. He also sees the utility of teaching the current prevalent tools: MPI and OpenMP, while remaining sensitive to the emerging potential standards: CUDA, OpenCL, Ct, map-reduce, etc.
</li>
</p>
<li> <strong>Bob Chesebrough</strong>, Intel, who sees the trouble in River City of a late introduction of parallelism to students, and of course recommends the "Think Method", in this case the "Think Parallel" method. Parallelism is all around and the key concepts can be conveyed without a computer.
</li>
</p>
<li>
<strong>Steve Parker</strong>, nVidia, who believes and has done many things. There needs to be a teaser to get you to come to the event. This is it.
</li>
</p>
<li>
<strong>Charlie Peck</strong>, Earlham College, who sees faculty education as key activity to get right, since many CS faculty have limited first hand experience with the myriad faces of parallelism. Involving students is a key part of this, for a unique form of learning takes place via an apprenticeship model of student involvement.
</li>
</ul>
<p>For several years now, we have been a parallel education working group composed of broad representation from industry, colleges/universities, hardware manufactures, and labs We are about to call ourselves something like "The Educational Alliance for a Parallel Future." I now know first hand what is involved in morphing from a working group to an alliance. When you are getting ready to make a tee-shirt, alliance ends up sounding sounding way cooler, and actually better reflects who we are. We will also be releasing a parallel crossword puzzle. This is not one solved in parallel, though it might be if someone is looking over your shoulder. The subject matter is of many things parallel. Stay tuned, we'll point you to it, once it debuts at SC09.</p>
<p></body><br />
</html></p>
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		</item>
		<item>
		<title>api and widget demo: cpu power connection mashed with video</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/28/api-and-widget-demo-cpu-power-connection-mashed-with-video/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/28/api-and-widget-demo-cpu-power-connection-mashed-with-video/#comments</comments>
		<pubDate>Wed, 28 Oct 2009 23:49:38 +0000</pubDate>
		<dc:creator>Andy Idsinga (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[Mashup]]></category>

		<category><![CDATA[video]]></category>

		<category><![CDATA[web]]></category>

		<category><![CDATA[web api]]></category>

		<category><![CDATA[web developer]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/28/api-and-widget-demo-cpu-power-connection-mashed-with-video/</guid>
		<description><![CDATA[Andy shares video versions of web API presentations he been making to web developers.]]></description>
			<content:encoded><![CDATA[<p>Here are a couple of presentations I've been making a lot lately - about our work to expose platform/device capabilities to web developers.</p>
<p>After you look at the technology, think about the kinds of device capabilities, hardware and software, that would make your web application better. Then share them with us - we're listening.<br />
If you need some food for thought <a href="http://software.intel.com/en-us/blogs/2009/10/22/api-drafts-posted-at-w3c-web-developer-comments-welcome/">take a look at this blog post</a> - where I list several API drafts we recently submitted to the <a href="http://www.w3.org/2009/dap/">W3C Device API working group</a>.</p>
<p>"The story" gives you the context. "The Technology" dives a little deeper into the details.</p>
<p><object width="640" height="505"><param name="movie" value="http://www.youtube.com/v/l05oJqo4C-A&#038;hl=en&#038;fs=1&#038;rel=0&#038;color1=0x3a3a3a&#038;color2=0x999999"></param><param name="allowFullScreen" value="true"></param><param name="allowscriptaccess" value="always"></param><embed src="http://www.youtube.com/v/l05oJqo4C-A&#038;hl=en&#038;fs=1&#038;rel=0&#038;color1=0x3a3a3a&#038;color2=0x999999" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="640" height="505"></embed></object></p>
<p><object width="640" height="505"><param name="movie" value="http://www.youtube.com/v/E-aFxj1MnKM&#038;hl=en&#038;fs=1&#038;rel=0&#038;color1=0x3a3a3a&#038;color2=0x999999"></param><param name="allowFullScreen" value="true"></param><param name="allowscriptaccess" value="always"></param><embed src="http://www.youtube.com/v/E-aFxj1MnKM&#038;hl=en&#038;fs=1&#038;rel=0&#038;color1=0x3a3a3a&#038;color2=0x999999" type="application/x-shockwave-flash" allowscriptaccess="always" allowfullscreen="true" width="640" height="505"></embed></object></p>
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		<item>
		<title>Memory management challenges in parallel applications</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/28/memory-management-challenges-in-parallel-applications/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/28/memory-management-challenges-in-parallel-applications/#comments</comments>
		<pubDate>Wed, 28 Oct 2009 14:18:00 +0000</pubDate>
		<dc:creator>Roman Lygin (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[Threading Building Blocks]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/28/memory-management-challenges-in-parallel-applications/</guid>
		<description><![CDATA[Let me share some recent practical experience with memory management issues when developing a multi-threaded application. This can probably be a rather common case (as recent post by Roman Dementiev and its follow up discussion demonstrates), and I’d be happy if my experience were helpful for others.
Working on CAD Exchanger I am designing one of [...]]]></description>
			<content:encoded><![CDATA[<p>Let me share some recent practical experience with memory management issues when developing a multi-threaded application. This can probably be a rather common case (as <a href="http://software.intel.com/en-us/blogs/2009/08/21/is-your-memory-management-multi-core-ready/">recent post by Roman Dementiev</a> and its follow up discussion demonstrates), and I’d be happy if my experience were helpful for others.</p>
<p>Working on <a href="http://www.cadexchanger.com">CAD Exchanger</a> I am designing one of its plugin to convert 3D CAD data between ACIS and Open CASCADE (two modeling kernels) to be parallel. Depending on a model size, the converter has to deal with multiple small objects allocated on a heap (e.g. 20,000+ objects each taking 48bytes + additional object data such as lists, strings, etc).</p>
<p>The translation works just fine and concurrency analysis with <a href="http://www.intel.com/go/parallel">Intel Parallel Amplifier</a> indicates high concurrency levels. So far, so good. However I had noticed that when translating the same ACIS file over and over again in the same test harness session translation took longer and longer. Why could it be ?</p>
<p>So I launched the Amplifier to collect hotspots and here is what I saw:</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-hostpot3.png"><img src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-hostpot3-300x87.png" alt="" width="300" height="87" class="aligncenter size-medium wp-image-11266" /></a></p>
<p>These two top hotspots relate to the memory manager layer (Standard_MMgrRaw class) which simply forwards calls to malloc/free and new/delete. Trying to root-cause the problem I had to switch to the mode to see direct OS functions (toggling off the button on the Amplifier toolbar) and here is a new screenshot:</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-hostpot4a.png"><img src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-hostpot4a-300x92.png" alt="" width="300" height="92" class="aligncenter size-medium wp-image-11264" /></a></p>
<p>It shows that hotspots are two system functions – RtlpFindAndCommitPages() and ZwWaitForSingleObject() – which are called from memory allocation / deallocation routines. It also shows that the nearest hotspot related to my code (BSplCLib::Bohm()) is just 1/4 of the time consumed by ZwWaitForSingleObject() (0.47s vs 1.81s).</p>
<p>After experimenting with several runs, analyzing how the hotspot profile changes with growing number of runs, I concluded that the first hotspot is explained by the fact that the ACIS converter creates multiple tiny objects with different size with short life span (they are destroyed after every conversion). This seems to cause strong memory fragmentation which forces the system to constantly look for new memory chunks.</p>
<p>The second hotspot (ZwWaitForSingleObject()) which goes through critical section is caused by the default mechanism of memory management on Windows <a href="http://msdn.microsoft.com/en-us/library/ms683476(VS.85).aspx">which uses a lock</a>.</p>
<p>The execution of locks&amp;waits analysis also proves that memory management lock is the greatest one adversely affecting concurrency.</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-lw2.png"><img src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-lw2-300x175.png" alt="" width="300" height="175" class="aligncenter size-medium wp-image-11265" /></a></p>
<p>All this is caused by the direct use of calloc/malloc/free, and new/delete called dozens of thousands times. It’s worth mentioning that such hotspots did not exist when I used serial implementation and popped up only when I started using parallel one. The former used a memory manager (in a 3rd party lib) that allocated memory blocks and did not return them to the system reusing them when the application requested new blocks. I couldn’t reuse this memory manager because it was not thread-safe and therefore had to switch to another manager that simply forwarded to malloc/free.</p>
<p>So I almost was forced to write my own memory manager that would implement a previous behavior and would be thread-safe and … fast ! Challenges are good but not when you need to re-write low-level components what can take a lot of time and require diligent thorough testing delaying progress in your project which already receives very limited attention.</p>
<p>So, I approached my colleagues from the Threading Build Blocks team to check if there is anything TBB could help with. What was my surprise when they suggested me trying a new release 2.2. Version 2.2 offers a mechanism to seamlessly replace the system memory manager with the tbb allocator. ‘Seamlessly’ really means it – everything I had to is to add a single line of code into a C++ file:</p>
<p>#include "tbb/tbbmalloc_proxy.h"</p>
<p>The outcome was immediate. Not only did the hotspot profile change completely removing the OS hotspots (see the comparison mode screenshot below) but the overall speed up (on entire test case) was about 25%! One line of code, no need of re-writing anything on my own saved hours of coding, with such a return! Just incredible, the least I could say. Recently released 2.2 Update 1 includes further improvements which my app now benefits from (more reliable processing of realloc(), bug fixes for debug mode, etc).</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-hostpot3.png"><img src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/mm-hostpot3-300x87.png" alt="" width="300" height="87" class="aligncenter size-medium wp-image-11266" /></a></p>
<p>The colleagues later explained me that the TBB allocator runs concurrently (seemingly without any locks inside) and with a similar fashion of reusing previously allocated blocks. Thus, it was the entire application (not only its parallel part) which benefited from this substitution. </p>
<p>So, if you are migrating from serial to parallel implementation you may encounter something unexpected – memory bottlenecks. If you got accustomed to use some nice single-threaded memory manager you can be forced to consider migration to something alternative. If this is the case you may want to give a try to tbb allocator and see if it helps in your case.</p>
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		</item>
		<item>
		<title>Check out this McCool event in December at UPCRC</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/22/check-out-this-mccool-event-in-december-at-upcrc/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/22/check-out-this-mccool-event-in-december-at-upcrc/#comments</comments>
		<pubDate>Fri, 23 Oct 2009 07:09:12 +0000</pubDate>
		<dc:creator>Rita Turkowski (Intel)</dc:creator>
		
		<category><![CDATA[Academic]]></category>

		<category><![CDATA[Cool Software]]></category>

		<category><![CDATA[Events]]></category>

		<category><![CDATA[Parallel Prog. &amp; Multi-Core]]></category>

		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/22/check-out-this-mccool-event-in-december-at-upcrc/</guid>
		<description><![CDATA[December 3rd at 4PM CST
12/3 &#124; 4PM &#124; 2405 Siebel Center for Computer Science
UPCRC Illinois Research Seminar: A Structured, Unified Approach to Multi-Core and Many-Core Computing - with Applications by Michael McCool, Intel &#38; U of Waterloo
]]></description>
			<content:encoded><![CDATA[<p><strong><span style="#17365d;">December 3rd at 4PM CST</span></strong></p>
<p class="MsoNormal"><strong><span style="x-small;"><span style="bold;">12/3 | 4PM | 2405 Siebel Center for Computer Science</span></span></strong></p>
<p class="MsoNormal"><span style="x-small;"><span style="9.5pt;"><a title="http://illinois.edu/calendar/Calendar?calId=2238&amp;eventId=144589&amp;ACTION=VIEW_EVENT" href="http://illinois.edu/calendar/Calendar?calId=2238&amp;eventId=144589&amp;ACTION=VIEW_EVENT"><span style="#0d0d0d;"><span style="#0d0d0d;" title="http://illinois.edu/calendar/Calendar?calId=2238&amp;eventId=144589&amp;ACTION=VIEW_EVENT"><span title="http://illinois.edu/calendar/Calendar?calId=2238&amp;eventId=144589&amp;ACTION=VIEW_EVENT">UPCRC Illinois Research Seminar: A Structured, Unified Approach to Multi-Core and Many-Core Computing - with Applications by Michael McCool, Intel &amp; U of Waterloo</span></span></span></a></span></span></p>
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		</item>
		<item>
		<title>API drafts posted at W3C - web developer comments welcome!</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/22/api-drafts-posted-at-w3c-web-developer-comments-welcome/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/22/api-drafts-posted-at-w3c-web-developer-comments-welcome/#comments</comments>
		<pubDate>Thu, 22 Oct 2009 19:16:06 +0000</pubDate>
		<dc:creator>Andy Idsinga (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[standards]]></category>

		<category><![CDATA[web]]></category>

		<category><![CDATA[web api]]></category>

		<category><![CDATA[web developer]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/22/api-drafts-posted-at-w3c-web-developer-comments-welcome/</guid>
		<description><![CDATA[Andy lists a set of device capability APIs that were posted at the WC3's Device API and Policy Working Group. These APIs are all about bringing better access to device hardware capabilities to web developers.]]></description>
			<content:encoded><![CDATA[<p>The other day ago our team, including <a href="http://software.intel.com/en-us/blogs/author/clayne-robison/">Clayne Robison</a> who also has a blog here on ISN, posted some <a href="http://dev.w3.org/2009/dap/system-info/Overview.html">API drafts</a> to the W3C's <a href="http://www.w3.org/2009/dap/">Device API and Policy Working Group</a>.</p>
<p>In a <a href="http://software.intel.com/en-us/blogs/2009/10/07/conversationstart-enabling-web-developers/">previous post</a> I kicked off a conversation with web developers about exposing device capabilities as javascript APIs and widgets in the browser.</p>
<p>Here's your chance to comment and help inform our web developer enabling activities. Tell us about how having better access to the device's hardware capabilities would make your web app implementation easier. Maybe you have a use case you would like to share?</p>
<p>Here is a list of APIs for device capabilities we proposed. </p>
<table rules="rows" cellpadding="1" style="width:95%;text-align:left;">
<tr style="border:1px dotted #cccccc;">
<th style="width:15%;">API</th>
<th style="width:85%;">Description</th>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Compass
    </td>
<td>
      Allows web apps to make use of a device's compass. The app can detect the<br />
      current orientation and receive asynchronous updates when the<br />
      orientation changes.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Power
    </td>
<td>
      Allows web apps to learn about the device's power state.<br />
      The app can detect the current power level, time remaining and receive<br />
      asynchronous updates about power level changes.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    CPU
    </td>
<td>
      Allows web apps to learn about the device's CPU - number of processors,<br />
      frequency, cpu usage levels.<br />
      The app can detect the current cpu usage and receive asynchronous<br />
      updates about cpu usage.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Display
    </td>
<td>
      Allows web apps to learn about the device's display capabilities - dots per inch,<br />
      supported orientations, brightness etc.<br />
      The app can detect the current orientation and brightness and receive<br />
      asynchronous updates about display orientation and brightness changes.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Connection
    </td>
<td>
      Allows web apps to learn about the device's network status and ability to<br />
      connect to services over the current network.<br />
      The app can detect check if an URL is reachable and check the latency<br />
      to and URL.<br />
      The app can receive asynchronous updates about network and service changes.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Thermal
    </td>
<td>
      Allows web apps to learn about thermometers connected to the device.<br />
      The app can detect the current temperature and receive asynchronous updates<br />
      about temperature changes.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Audio
    </td>
<td>
      Allows web apps to learn about the device's audio capabilities.<br />
      The app can determine which audio codecs are installed. The app can<br />
      also learn about speakers, microphones, lines in and lines out.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Video
    </td>
<td>
      Allows web apps to learn about the device's video capabilities.<br />
      The app can determine which video codecs are installed and what formats<br />
      and profiles they support. The app can also determine if codecs support<br />
      hardware acceleration.
    </td>
</tr>
<tr style="border:1px dotted #cccccc;">
<td>
    Input
    </td>
<td>
      Allows web apps to learn about the device's user input capabilities.<br />
      The app can determine if the device has a touch screen, if it<br />
      has multi-touch support, if a physical keyboard is present or if a software<br />
      keyboard is visible. The app can receive asynchronous updates about<br />
      physical keyboard attach / detach. The app can receive asynchronous updates<br />
      about physical pointer attach / detach.
    </td>
</tr>
</table>
<p>You can see the detailed API specs and example use cases at the <a href="http://dev.w3.org/2009/dap/system-info/Overview.html">WC3's site</a>.<br />
<strong>This is only the beginning</strong>. Stay tuned to the blog, or <a href="http://twitter.com/andyidsinga">my tweets</a>, for more API, widget and mashup proposals coming in the near future.</p>
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		<item>
		<title>Search of explicit type conversion errors in 64-bit programs</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/22/search-of-explicit-type-conversion-errors-in-64-bit-programs/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/22/search-of-explicit-type-conversion-errors-in-64-bit-programs/#comments</comments>
		<pubDate>Thu, 22 Oct 2009 16:21:15 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[64-bit]]></category>

		<category><![CDATA[64-bit Coding]]></category>

		<category><![CDATA[64-bit migration]]></category>

		<category><![CDATA[C++]]></category>

		<category><![CDATA[Viva64]]></category>

		<category><![CDATA[x64]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/22/search-of-explicit-type-conversion-errors-in-64-bit-programs/</guid>
		<description><![CDATA[On forums I'm constantly asked questions concerning search of incorrect explicit type conversion when porting code on a 64-bit platform. I decided to write this small note so that I could refer people to it and avoid writing the answer every time.]]></description>
			<content:encoded><![CDATA[<p>On forums I'm constantly asked questions concerning search of incorrect explicit type conversion when porting code on a 64-bit platform. I decided to write this small note so that I could refer people to it and avoid writing the answer every time.The description of the problem looks approximately as shown below:</p>
<p>"Debugging bad pointer casts in 64bits"<br />
I am currently converting a program to Windows 64bits. Some bad code casts<br />
pointers into long and vice-versa.<br />
Code example:</p>
<pre>MyObj* pObj = …
  ::SendMessage(hwnd, msg, (WORD)x, (DWORD)pObj);</pre>
<p>The problem is that it is impossible to detect such errors with the help of the compiler as explicit type conversion is used which suppresses diagnostic messages. The static code analyzer <a href="http://www.viva64.com/viva64-tool/">Viva64</a> is used for diagnosing these and many other errors.</p>
<p>Viva64 is a specialized commercial tool for searching errors in C/C++ programs when porting them on 64-bit systems or developing new 64-bit programs. Besides, the tool allows you to better optimize 64-bit code. The tool is rather expensive but our users can get support in setting and improving the tool according to the peculiarities of their projects what makes the tool very effective.</p>
<p>This tool serves for detecting explicit type conversions which are dangerous from the viewpoint of a 64-bit data model.</p>
<p>For example, on the code given above the analyzer will show warning V202:<br />
<a href="http://www.viva64.com/content/PVS-Studio-help-en/V202.html">V202. Explicit type conversion. Type casting from memsize to 32-bit.</a></p>
<p>And on the following code where incorrect explicit type conversion from a 32-bit to a 64-bit type is used:</p>
<pre>unsigned width, height, depth;
DWORD_PTR arraySize = DWORD_PTR (width * height * depth);</pre>
<p>you'll get warning V201:<br />
<a href="http://www.viva64.com/content/PVS-Studio-help-en/V202.html">V201. Explicit type conversion. Type casting to memsize.</a></p>
<p>Conclusion: if you have a large code it is more reasonable not to perform eternal testing catching new overflows/cut of values at the next set of input data but to buy Viva64 and catch these errors at the very early stages.</p>
<p>The analyzer considers the last fragment of the code suspicious, as it is very similar to a typical error. The fact is, that if width, height and depth meanings are quite large, during multiplication, 32-bit type unsigned overflow can occur. And this incorrect result will be expanded to 64-bit DWORD_PTR type and placed in arraySize variable. There is high probability that the code should be rewritten in the following way:</p>
<pre>unsigned width, height, depth;
DWORD_PTR arraySize = DWORD_PTR (width) *
  DWORD_PTR (height) * DWORD_PTR (depth);</pre>
<p>In this case, 64-bit types will be multiplied, and the overflow will disappear. Such situations are described in detail in the article "<a href="http://www.viva64.com/art-1-2-599168895.html">20 Issues of Porting C++ Code on the 64-bit Platform</a>".</p>
<p>Additional links:</p>
<ul>
<li>Viva64: what is it and for whom is it meant?<br />
<a href="http://www.viva64.com/art-1-2-903037923.html">http://www.viva64.com/art-1-2-903037923.html</a></li>
<li>64 bits, Wp64, Visual Studio 2008, Viva64 and all the rest…<br />
<a href="http://www.viva64.com/art-1-2-621693540.html">http://www.viva64.com/art-1-2-621693540.html</a></li>
</ul>
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		</item>
		<item>
		<title>Visual Studio 2010 Beta 2 + Silverlight 3.0 SDK</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/21/visual-studio-2010-beta-2-silverlight-30-sdk/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/21/visual-studio-2010-beta-2-silverlight-30-sdk/#comments</comments>
		<pubDate>Wed, 21 Oct 2009 22:05:52 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/21/visual-studio-2010-beta-2-silverlight-30-sdk/</guid>
		<description><![CDATA[
Silverlight 3.0 development is supported within Visual Studio 2010 and it includes the Silverlight 3 developer runtime and Silverlight 3 SDK build 3.0.40818.
Silverlight 3 tools for Visual Studio 2008 and Expression Blend 3 included SDK build 3.0.40624 and if these are installed when you run the Visual Studio 2010 beta 2 installer an error will be [...]]]></description>
			<content:encoded><![CDATA[<p><img class="alignnone size-full wp-image-10838" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/visualstudio.jpg" alt="" width="500" height="135" /></p>
<p>Silverlight 3.0 development is supported within Visual Studio 2010 and it includes the Silverlight 3 developer runtime and <a href="http://go2.microsoft.com/fwlink/?LinkID=157102">Silverlight 3 SDK</a> build 3.0.40818.</p>
<p>Silverlight 3 tools for Visual Studio 2008 and Expression Blend 3 included SDK build 3.0.40624 and if these are installed when you run the Visual Studio 2010 beta 2 installer an error will be reported. Fear not however and refer to the blog post by <a href="http://blogs.msdn.com/amyd/archive/2009/10/21/visual-studio-2010-and-silverlight-3-sdk.aspx" target="_blank">Amy Dollard</a> on MSDN.</p>
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		<item>
		<title>Windows 7 + Intel Core i7 Mobile Processor + 16Gb Memory</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/21/windows-7-intel-core-i7-mobile-processor-16gb-memory/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/21/windows-7-intel-core-i7-mobile-processor-16gb-memory/#comments</comments>
		<pubDate>Wed, 21 Oct 2009 20:58:00 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Intel® Atom™ Developer Program]]></category>

		<category><![CDATA[Parallel Prog. &amp; Multi-Core]]></category>

		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[Virtualization]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/21/windows-7-intel-core-i7-mobile-processor-16gb-memory/</guid>
		<description><![CDATA[
We have only 24 hours left until the General Availability (GA) of Windows 7 and so tomorrow Windows 7 will be in the hands of consumers for the first time. With the release of Windows 7, along with the release of some awesome new processors from Intel, it was time for a new personal notebook and also for a companion netbook [...]]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.amazon.com/gp/redirect.html?ie=UTF8&amp;location=http%3A%2F%2Fwww.amazon.com%2Fgp%2Ffeature.html%3Fie%3DUTF8%26ref%255F%3Dms%255Fsbrspot%255F2%26docId%3D1000392481&amp;tag=sofbloint-20&amp;linkCode=ur2&amp;camp=1789&amp;creative=390957" target="_blank"><img class="alignnone size-medium wp-image-7713" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/06/windows7rtm-300x300.jpg" alt="" width="300" height="300" /></a></p>
<p>We have only 24 hours left until the General Availability (GA) of <a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a> and so tomorrow <a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a> will be in the hands of consumers for the first time. With the release of <a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a>, along with the release of some awesome new processors from Intel, it was time for a new personal notebook and also for a companion netbook as <a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a> has been designed to work great on netbooks.</p>
<p>If you've been following this blog for sometime you'll know that I use Hyper-V for virtualization within <a href="http://www.microsoft.com/windowsserver2008/en/us/r2.aspx" target="_blank">Windows Server 2008 R2</a>, the server variant of <a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a>, with this in mind I found the <a href="https://www.amazon.com/dp/B002TMR7U8?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=B002TMR7U8&amp;adid=119AX3ZPAG4AZQ6VCHN1&amp;" target="_blank">HP Envy 15</a>. Inside this machine is the mobile <a href="http://www.intel.com/products/processor/corei7/mobile/index.htm" target="_blank">Core i7</a> processor which is quad-core and supports hyper-threading allowing the execution of 8 concurrent threads, and for virtualization there is 16Gb of DDR3 memory.</p>
<p><a href="https://www.amazon.com/dp/B002TMR7U8?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=B002TMR7U8&amp;adid=119AX3ZPAG4AZQ6VCHN1"><img class="alignnone size-medium wp-image-10952" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/hp-envy-15-12-300x205.jpg" alt="" width="300" height="205" /></a><img class="alignnone size-full wp-image-10955" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/ci7_62.gif" alt="" width="62" height="76" /></p>
<p>I also ordered the <a href="https://www.amazon.com/dp/B002ONCBVC?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=B002ONCBVC&amp;adid=1FD45HK16ZK8RAG4S3NS&amp;" target="_blank">HP Mini 311</a> which is powered by an Intel <a href="http://www.intel.com/technology/atom/index.htm" target="_blank">Atom</a> processor as a companion device that can be used when travelling. I chose this netbook over others on the market because you can install 3Gb of DDR3 memory. </p>
<p><a href="https://www.amazon.com/dp/B002ONCBVC?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=B002ONCBVC&amp;adid=1JMTYVQRPCCB9ZSVT1NR"><img class="alignnone size-medium wp-image-10951" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/hpmini311-300x230.jpg" alt="" width="300" height="230" /></a><img class="alignnone size-full wp-image-10956" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/atom_62.gif" alt="" width="62" height="76" /></p>
<p>I'll be blogging next month about the experience of <a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a> on both the <a href="http://www.intel.com/products/processor/corei7/mobile/index.htm" target="_blank">Core i7</a> and <a href="http://www.intel.com/technology/atom/index.htm" target="_blank">Atom</a> processors, specifically with the software developer in mind.</p>
<p>It should also be mentioned that this blog post does not represent an endoresemnt, by <a href="http://www.intel.com" target="_blank">Intel Corporation</a>, of the particular laptop and netbook models shown above. I purchased these machines based on my own research and my own requirements.</p>
<p><a href="http://www.microsoft.com/windows/windows-7/default.aspx" target="_blank">Windows 7</a> is an outstanding operating system (imho) and I'd be very interested to hear what you think of the operating system and the <a href="http://www.intel.com/products/processor/corei7/mobile/index.htm" target="_blank">Core i7</a> and <a href="http://www.intel.com/technology/atom/index.htm" target="_blank">Atom</a> processors.</p>
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		<item>
		<title>Microsoft PDC 2009 = Visual Studio 2010 Beta 2 + RIA Services</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/20/microsoft-pdc-2009-visual-studio-2010-beta-2-ria-services/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/20/microsoft-pdc-2009-visual-studio-2010-beta-2-ria-services/#comments</comments>
		<pubDate>Tue, 20 Oct 2009 16:22:47 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/20/microsoft-pdc-2009-visual-studio-2010-beta-2-ria-services/</guid>
		<description><![CDATA[
Yesterday beta 2 of Visual Studio 2010 was released and Microsoft confirmed that the official launch date for Visual Studio 2010 will be March 22, 2010.
After downloading the build one notable absentee was RIA Services although according to Brad Abrams the support for RIA services will be available at the PDC next month.
]]></description>
			<content:encoded><![CDATA[<p><img class="alignnone size-full wp-image-10838" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/visualstudio.jpg" alt="" width="500" height="135" /></p>
<p>Yesterday beta 2 of <a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> was released and Microsoft confirmed that the official launch date for <a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> will be March 22, 2010.</p>
<p>After downloading the build one notable absentee was <a href="http://blogs.msdn.com/brada/archive/2009/03/19/what-is-net-ria-services.aspx" target="_blank">RIA Services</a> although according to <a href="http://blogs.msdn.com/brada/default.aspx" target="_blank">Brad Abrams</a> the support for <a href="http://blogs.msdn.com/brada/archive/2009/03/19/what-is-net-ria-services.aspx" target="_blank">RIA services</a> will be available at the <a href="http://www.microsoftpdc.com" target="_blank">PDC</a> next month.</p>
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		<title>ISAs and APIs, an Analogy</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/19/isas-and-apis-an-analogy/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/19/isas-and-apis-an-analogy/#comments</comments>
		<pubDate>Mon, 19 Oct 2009 21:38:46 +0000</pubDate>
		<dc:creator>Peter Nee (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/19/isas-and-apis-an-analogy/</guid>
		<description><![CDATA[“Library design is language design.”
	Bell Labs proverb as told by Bjarne Stroustrup
Bjarne Stroustrup, creator and champion of the C++ language, is among other things a collector of aphorisms, and this is one of his favorites. It’s a deep idea, but I want to touch on just one aspect of this surprising equivalence, and tie it [...]]]></description>
			<content:encoded><![CDATA[<p>“Library design is language design.”<br />
	Bell Labs proverb as told by Bjarne Stroustrup</p>
<p>Bjarne Stroustrup, creator and champion of the C++ language, is among other things a collector of aphorisms, and this is one of his favorites. It’s a deep idea, but I want to touch on just one aspect of this surprising equivalence, and tie it to, of all things, the <a href="http://www.intel.com/Assets/PDF/manual/248966.pdf">Intel Optimization Reference</a>.</p>
<p>The commonality I’m thinking of is the concept of deprecation. One thing that languages and libraries (or APIs if you prefer) share is that they are snapshots of what seems to be the best possible set of tools and concepts for solving problems in a specific domain. There’s an art of doing this well, because it requires thinking deeply with imperfect knowledge of the future. So, no library (or language) is perfect. All libraries can have features with flaws, and when a flaw becomes obvious enough, it can be addressed with some alternative feature that provides the functionality of the flawed original.</p>
<p>A classic example from the C runtime library are the string functions, such as strcpy(). strcpy() works on null-terminated strings of arbitrary length. This seemed simple, performant, and straightforward at the time the first C runtime libraries were created, but the lack of a “safety net” if a null terminator was omitted made it not just a painful source of errors, but also an ally of malicious coders. If a virus writer could guess you were using strcpy() behind a secure API, he or she was one step closer to a successful buffer overrun exploit.</p>
<p>So, strncpy() was created. It provides a safety net in the form a length parameter that the copy operation won’t exceed. All strcpy() calls should be replaced by strncpy() because of this advantage. But, the vast existing codebase cannot be cannot be changed overnight.</p>
<p>So, deprecation is the answer. It’s a policy that depends on developer compliance for success. New code should always use the new method (e.g., strncpy()) existing code should be updated whenever possible. Tools like compilers may be adapted to warn about the continuing presence of deprecated functions like strcpy(), but those functions will continue to work as designed.</p>
<p>In many cases, a large application may be updated to remove flawed APIs only in stages, over time. If a function or module is being updated for some other purpose, a new feature for example, a careful developer will take the opportunity to remove or replace deprecated library calls.</p>
<p>Languages too, can have deprecated features. And in the case of an assembly language, the most interesting of those “features” are typically instructions or instruction sequences that should be avoided for performance reasons.  In this sense, the language is really the Instruction Set Architecture itself. And this is where the Intel Optimization guide comes in. For example, Assembly/Compiler Coding Rules 28-31 from the Optimization Reference address the issue of instruction selection, and Rule 31 calls out by name instructions like Enter and Loop that should be avoided altogether.</p>
<p>Very few developers are creating new assembly routines anymore. Compiler quality and intrinsics support have greatly reduced the need for new assembly code. But there is a significant existing codebase out there. An existing assembly function may be opened up for changes, but not wholesale replacement. I have been in this situation several times in my career. If you are a developer working on such a function, the assembly coding rules in the optimization are your friend.</p>
<p>Just as you might replace deprecated library calls in a C function you are updating, the assembly coding rules can help you identify “deprecated” assembly code instructions that can be replaced with straightforward equivalents that will have better performance on current CPUs and those in the foreseeable future. And just as a development tool can call attention to deprecated APIs, performance analysis tools such as Intel VTune can flag assembly instructions that should be avoided.</p>
<p>Intel doesn’t technically call such instructions “deprecated”. In part that’s because deprecation implies eventual removal, and that’s far more problematic prospect for an ISA than for most libraries. But the principle is the same, and I hope that the parallels are compelling and clarifying.</p>
<p>My next few posts will call out some specific assembly coding rules from the optimization guide, and how those rules fit in with this analogy to API deprecation.</p>
<p>In the meantime, ponder the common sentiment shared by library designers, language designers, and instruction set architects when they reflect on those features they created which did not age gracefully, “It seemed like a good idea at the time”.</p>
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		<title>Download Visual Studio 2010 Beta 2 - Official Launch March 22, 2010</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/19/download-visual-studio-2010-beta-2-official-launch-march-22-2010/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/19/download-visual-studio-2010-beta-2-official-launch-march-22-2010/#comments</comments>
		<pubDate>Mon, 19 Oct 2009 16:56:59 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/19/download-visual-studio-2010-beta-2-official-launch-march-22-2010/</guid>
		<description><![CDATA[
Microsoft today released beta 2 of Visual Studio 2010 and confirmed that the official launch date for Visual Studio 2010 will be March 22, 2010.
Visual Studio 2010 beta 2 was uploaded to MSDN subscriber downloads shortly after 9am PST this morning and this build includes a "go-live" license. You can read more about the release [...]]]></description>
			<content:encoded><![CDATA[<p><img class="alignnone size-full wp-image-10838" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/visualstudio.jpg" alt="" width="500" height="135" /></p>
<p>Microsoft today released beta 2 of <a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> and confirmed that the official launch date for Visual Studio 2010 will be March 22, 2010.</p>
<p><a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> beta 2 was uploaded to MSDN subscriber downloads shortly after 9am PST this morning and this build includes a "go-live" license. You can read more about the release on Somasegar's blog <a href="http://blogs.msdn.com/somasegar/archive/2009/10/19/announcing-visual-studio-2010-and-net-fx-4-beta-2.aspx" target="_blank">here</a>.</p>
<p>Visual Studio Team Suite has been renamed Visual Studio 2010 Ultimate and the product also includes a new logo that is very similar to the mathematical infiniti symbol.</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/vs2010-splash.jpg"><img class="alignnone size-medium wp-image-10839" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/vs2010-splash-300x187.jpg" alt="" width="300" height="187" /></a></p>
<p>MSDN also seems to have a new logo too...</p>
<p><img class="alignnone size-medium wp-image-10842" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/lightbox_msdn_logo.png" alt="" width="199" height="52" /></p>
<p>Once opened, the <a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> environment can be seen here with the revised New Project dialog.</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/vs2010.jpg"><img class="alignnone size-medium wp-image-10841" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/vs2010-300x187.jpg" alt="" width="300" height="187" /></a></p>
<p>If you're interested in the build numbers of <a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> and the associated .net framework here is the about dialog.</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/vs2010-about.jpg"><img class="alignnone size-medium wp-image-10840" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/vs2010-about-300x224.jpg" alt="" width="300" height="224" /></a></p>
<p>Over the next few days and weeks I'll post extensively about <a href="http://www.microsoft.com/visualstudio/en-us/products/2010/default.mspx" target="_blank">Visual Studio 2010</a> and Team Foundation Server 2010.</p>
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		<title>Ineffectiveness of last() in the real world</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/19/ineffectiveness-of-last-in-the-real-world/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/19/ineffectiveness-of-last-in-the-real-world/#comments</comments>
		<pubDate>Mon, 19 Oct 2009 16:19:34 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[C++]]></category>

		<category><![CDATA[Viva64]]></category>

		<category><![CDATA[VivaCore]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/19/ineffectiveness-of-last-in-the-real-world/</guid>
		<description><![CDATA[While studying at the institute and learning different data processing algorithms, I already knew that the necessity of using such a function as last() for one-way list can indicate an unfortunate choice of the data structure and lead to ineffective algorithm. Although I knew it long ago, I haven’t faced this in practice until recently.]]></description>
			<content:encoded><![CDATA[<p>While studying at the institute and learning different data processing algorithms, I already knew that the necessity of using such a function as last() for one-way list can indicate an unfortunate choice of the data structure and lead to ineffective algorithm. Although I knew it long ago, I haven’t faced this in practice until recently.</p>
<p>It began with a complaint that the static analyzer <a href="http://viva64.com/viva64-tool/">Viva64</a> hangs when analyzing one project, or rather one file of the project. Analysis showed that the analyzer doesn’t hang at all and on the contrary works very hard. Very hard and very long. I think even this analyzer can analyze it successfully in approximately 5 or 10 hours :). But this became clear later and of course such behavior should be considered an error.</p>
<p>Frankly speaking, at the beginning I was astonished by this behavior. Viva64 analyzer operates rather quickly, and average time of analyzing one file takes just a few seconds. And its operating time is much less than time needed for preprocessing files. Preprocessing is executed by Visual C++ compiler and we cannot speed up this process yet. That’s why, roughly speaking, the time of testing a project is close to the time of preprocessing all the files. And suddenly we discover such a great ineffectiveness in the analysis algorithm!</p>
<p>Investigations showed that hanging occurs when processing the file which contains some resources from Qt library, more exactly array whose size… well, I don’t know its size, but I know that this is the largest array I’ve ever seen. It looks as follows:</p>
<pre>static const unsigned char qt_resource_data[] = {
  0x0,0x0,0x0,0xc5,
  0x51,
  0x46,0x72,0x61,0x6d,0x65,0x20,0x7b,
  0xd,0xa,0x20,0x20,0x20,0x20,0x6d,0x69,0x6e,
  0x2d,0x77,0x69,0x64,0x74,0x68,0x3a,0x20,
  0x36,0x70,0x78,0x3b,0xd,0xa,0x20,0x20,
  0x20,0x20,0x6d,0x69,0x6e,0x2d,0x68,0x65,
  0x69,0x67,0x68,0x74,0x3a,0x20,0x36,0x30,
  . . .</pre>
<p>This array occupies about 9 Mb in the file. This is a lot but it’s not reason for the analyzer for such a bad behavior.</p>
<p>The problem was the already mentioned last() function. Viva64 analyzer is built on <a href="http://viva64.com/vivacore-library/">VivaCore</a> library. And VivaCore is built in its turn on OpenC++ library from which it inherited data representation as trees and lists. By the way, data processing in OpenC++ (and VivaCore as well) reminds a lisp program very much. There are a lot of functions of the type like Eq, Car, Cdr, First, Rest, Second, Nth, List etc.</p>
<p>And there is also last() function which is used when creating a list of items for initializing the array. In the pseudocode it looks like this:</p>
<pre>while (some items still remain)
{
  Ptree *e = to take another item;
  Ptree *last = Last(eList);
  last-&gt;SetCdr(Cons(e, 0));
}</pre>
<p>In general the point is to take the following array’s item and add it to the end of the list. To simplify search of the end we use last() function. OpenC++’s author obviously didn’t suggest that the algorithm will be forced to process the array of millions of items. On small arrays it’s OK, but to the time of such an algorithm increases in proportion to the squared number of items (to be more exact - the triangular number 0.5 * n * (n + 1), where n is the number of items).</p>
<p>The simplest optimization consisting in keeping the pointer to the last item of the list (what allows you not to call last() function) literally worked a miracle. Processing of the file which earlier took more than 3 hours (I didn’t manage to wait more than 3 hours :), now takes several seconds.</p>
<p>Well, all we can say - be careful before you use functions like last(). You can never tell what your algorithm will be sooner or later palmed off. I wish you luck in optimization!</p>
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		<title>SQL Server 2008 - SQLCLR .NET Framework Version</title>
		<link>http://software.intel.com/en-us/blogs/2009/10/16/sql-server-2008-sqlclr-net-framework-version/</link>
		<comments>http://software.intel.com/en-us/blogs/2009/10/16/sql-server-2008-sqlclr-net-framework-version/#comments</comments>
		<pubDate>Fri, 16 Oct 2009 19:28:13 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2009/10/16/sql-server-2008-sqlclr-net-framework-version/</guid>
		<description><![CDATA[
Since SQL Server 2005 we have had the ability to write User Defined Types (UDT's) and User Defined Aggregates (UDA's) etc. with the C# programming language that are executed by the .net framework CLR that is loaded within the SQL Server process.
In SQL Server 2008 the latest service release of the .net framework CLR version 2.0 is [...]]]></description>
			<content:encoded><![CDATA[<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/sqlclr-views.jpg"></a><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/200px-net_h_rgb_2.png"><img class="alignnone size-full wp-image-10798" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/200px-net_h_rgb_2.png" alt="" width="200" height="49" /></a></p>
<p>Since SQL Server 2005 we have had the ability to write <a href="http://technet.microsoft.com/en-us/library/ms131120(SQL.90).aspx" target="_blank">User Defined Types</a> (UDT's) and <a href="http://technet.microsoft.com/en-us/library/ms131057(SQL.90).aspx" target="_blank">User Defined Aggregates</a> (UDA's) etc. with the C# programming language that are executed by the .net framework CLR that is loaded within the SQL Server process.</p>
<p>In SQL Server 2008 the latest service release of the .net framework CLR version 2.0 is loaded within the SQL Server process. Given that the .net framework 4.0 introduces a new version of the CLR, which CLR be loaded by SQL Server if both the 2.0 and 4.0 CLR's are installed?</p>
<p>SQL Server 2008 and the forthcoming SQL Server 2008 R2 release, previously codenamed "Kilimanjaro", will both continue to load the latest service release of the version 2.0 CLR.</p>
<p>You might be wondering, what is the rationale behind SQL Server continuing to load version 2.0 of the CLR? Is it merely a healthy cautious attitude so existing UDT's, UDA's, etc. are not broken; or is it because additional engineering would be required to support the new CLR?</p>
<p>It seems the answer is actually a little of both.</p>
<p>With the .net framework 4.0 we now have the ability to load two or more distinct versions of the CLR within a single process. In previous releases of the .net framework, a process could only load a single instance of the CLR. Given this restriction the CLR team recommended that hosts, such as SQL Server, use the <a href="http://msdn.microsoft.com/en-us/library/ms230241.aspx" target="_blank">LockClrVersion</a> function to determine the version of the CLR to load prior to initialization. So, as stated previously, SQL Server 2008 and SQL Server 2008 R2 will continue to load the latest service release of the version 2.0 CLR as the version is locked before initialization of the CLR begins.</p>
<p>While future versions of SQL Server may load newer versions of the CLR, or even support the loading of multiple CLR's within the process, version 2.0 of the CLR is here to stay for SQLCLR within SQL Server 2008 and SQL Server 2008 R2.</p>
<p>If you're looking for more information on programming within SQL Server using the .net framework you should read <a href="https://www.amazon.com/dp/1590595661?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=1590595661&amp;adid=0HNADPM6GMK5H9VAMKM3&amp;" target="_blank">Pro SQL Server 2005 Assemblies</a> by Robbin Dewson and Julian Skinner. Other great books with content related to SQL CLR include <a href="https://www.amazon.com/dp/0735626022?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=0735626022&amp;adid=0RQ2WQV5ZGR7PXWKMB4R&amp;" target="_blank">Inside Microsoft SQL Server 2008: T-SQL Programming</a> by Itzik Ben-Gan and <a href="https://www.amazon.com/dp/0735625999?tag=sofbloint-20&amp;camp=213381&amp;creative=390973&amp;linkCode=as4&amp;creativeASIN=0735625999&amp;adid=1EK6P15SJAQDJ6E5VBQC&amp;" target="_blank">Programming Microsoft SQL Server 2008</a> by Leonard Lobel, Andrew J Brust, and Stephen Forte.</p>
<p>Within the SQL Server 2008 Management Studio you can determine the current CLR version by executing the following query against the sys.dm_clr_properties view.</p>
<p><code>select * from sys.dm_clr_properties</code></p>
<p>Views are also available within SQL Server 2008 to determine information regarding the application domains, loaded assemblies, and tasks. The results of executing these queries can be seen in Microsoft SQL Server Management Studio below.</p>
<p><code>select * from sys.dm_clr_appdomains</code><br />
<code>select * from sys.dm_clr_loaded_assemblies</code><br />
<code>select * from sys.dm_clr_tasks</code></p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/sqlclr-views1.jpg"><img class="alignnone size-full wp-image-10800" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2009/10/sqlclr-views1.jpg" alt="" width="500" height="278" /></a></p>
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