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Boost Your Skills with Intel's new Guide for Developing Multithreaded Applications
If you're coding for multicore, you shoot for maximum performance but hit barriers along the way. Arm yourself with the latest development and optimization tips from the experts.
Intel® Xeon Phi™ Coprocessor Technology Conference Presentations
- Intel® Xeon Phi™ Coprocessor Architecture Overview
- Stepwise Optimization Framework
- Leveraging Optimized Tools and Libraries
- Scalar and Serial Optimization
- Scale from Intel® Xeon® Processor to Intel® Xeon Phi™ Coprocessors
- MPSS – The Software Stack
- Source code for use with these presentations (iXPTC13v5.tar)
Low Latency Corner
Hardware, Software and Bios Parameters
- FSI Frequently Asked Questions
- "Configuring and Tuning HP ProLiant Servers for Low-Latency Applications" White Paper
- Low Latency Settings for Dell* Machines
- Red Hat Low Latency Turning Guide (RHN access required)
- General Haswell Site
- Haswell Instructions Set: including AVX2 Instructions
- Haswell TSX for transactions locks instructions and ways to test them with Intel PCM and Linux perf
Migrating to Intel Architecture
Monte Carlo Demo
This demo shows how to benefit from Xeon multi-core architecture using Intel Tools. It shows incremental gains for the application due to Intel compiler, Math Kernel Libraries and OpenMP respectively. This has been achieved by minimal changes to the original CPU code.
The demo requires the installation of .NET framework which is included in the bundle.