Intel Software Network - feed

help on detecting stalls(identifying structural hazards) in assembly code

Wed, 28 Oct 2009 10:18:15 -0700

Hi All,
Our project is to optimize instruction scheduling in gcc by detecting structural hazards. We are trying to come up with a test case for the same, a scenario wherein one of the instructions is stalled due to the resource being used by some other instruction. However, we are unable to do so.

1. We wrote a C program - doing - floating point multiplications, divisions and additions. However in both the files - 'progname.s' file and 'progname.c.190r.sched2' file, the instructions were scheduled for execution in sequential order. We couldn't find a way to detect a stall, by looking at the assembly code generated.
Question: How do we detect that a stall has occurred if execution is being carried out in a particular sequence?
Also we would like to know of a tool, which given a 'progname.s' file, gives details of the execution time of each instruction and the clock cycle in which stall will occur, if execution is carried out in this sequence.

2. We saw that integer operations were already being performed during compilation. Hence we were left with only floating point operations to be looked into for structural hazards.
Question: Once a stall is detected in case of floating point unit being used currently by some other instruction, which instruction can be scheduled in so as to avoid this stall(since integer operations are performed at compile time and floating point units are being used)?

Target machine architecture: 686
Working on: Intel Pentium Dual Core processor

Thanking you,
Dhiraj

is there a standard format in which we provide architecture specific information to a software

Sun, 25 Oct 2009 16:24:53 -0700

Hi All,
Our project requires us to specify architecture specific information to gcc(not .md files in gcc). We need to specify number of cycles taken per instruction for 686 architecture - as information to gcc.

Question: Is there a standard format in which we define the architecture specific information to softwares requiring these? Do we have the architecture specific information for Pentium Dual Core architecture in a format, that can be read by any software requiring it?

Target Architecture: 686 processor
Working on: Intel Pentium Dual Core processor

Thanking You,
Dhiraj.

how to turn off out-of-order execution in Intel processor

Sun, 25 Oct 2009 14:32:29 -0700

Hi All,
Our project is to optimize instruction scheduling in gcc, by detecting structural hazards. The algorithm employed requires no out-of-order executions by the processor.

Question: Is there a command/mechanism to turn out-of-order execution off in Intel processor?
Target Architecture: 686 processor
Working on: Intel Pentium Dual Core processor

Thanking You,
Dhiraj.

Parallel instructions for detecting MSB in array of bytes

Fri, 16 Oct 2009 01:58:32 -0700

First time posting, not sure if correct forum, but...

I have a large array of bytes, max up to 1600, but mostly up to 128.

Bytes are typically 7-bit of information, and the MSB is used as a sentinel, so the MSB is set in a small portion of the bytes.

Currently I'm looping through them in a loop, but is there a better way to use SSEx to process 128 bytes in parallel and get back a SSE vector with bits set for each byte?

Any suggestions?

Thank you,
craptacus

Why only CS, IP and EFLAGS are saved while interrupt??

Fri, 16 Oct 2009 01:34:34 -0700

I am new to assembly programming. I was reading about 386 Interrupt. I came to know that only CS, IP and EFLAGS are saved as a part of interrupt, they pop back when we have iret. But I am wondering, why they didnt save all the visible registers, segments register etc.,???

Please excuse me, if I understood something wrong.

Thanks for your effort in helping me...

Out of order execution

Thu, 15 Oct 2009 23:53:15 -0700

Is there a simulator and/or a general procedure one can follow to predict what instructions will be executed in what order (assuming all data is in the L1 cache)? I'm having a hard time comprehending why a given instruction sequence executes much faster than another. I suspect it's due to the out of order execution and register renaming, but I've found no tangible reason yet. Any help would be appreciated.

[smp] processor disabled

Thu, 15 Oct 2009 11:13:42 -0700

Hi,
I am trying to manage the multiprocessor initialization.

I found a little program [1] that implements the multiprocessor specification [2]. but in the processor entries([2] page 4-7) I get that the APs are disabled.

How can I enable the processors??
Is it a SW or HW problem ?

[1] http://www.uruk.org/mps/
[2] http://www.intel.com/design/pentium/datashts/242016.HTM

Thank you.
Daniel M.

LZCNT on Core i7

Mon, 12 Oct 2009 04:29:45 -0700

Let me start with: I know that LZCNT is not supported on the Core i7.

However when I run theinstruction on my Core i7 I do not as I expect get an illegal instruction exception.
Instead it performs a BSR instruction.
This is while working in 64 bit mode and using 64 bit registers.

Is this a bug, expected behaior or is running unsupported instructions undefined (and this is therefore OK)?

For reference the opcodes are:
BSR: 0xBD
LZCNT: 0xBD (Same as BSR but has a prefix of 0xF3)

Any feedback would be helpful.

CJ.

How to multiply __m128 by a scaler?

Wed, 30 Sep 2009 11:30:11 -0700

I am just starting to work with the SSE intrinsic functions. Is there a better way to mupltiply a vector V by a scalar A than what I am doing below?

I would like to do the following u = u + (v*1.5 - vold*0.5)*delta_t;

where u, v, and vold are a vector with x, y, z, coordinates represented in a __m128.

Is there a better way to do this than to create the a, b and c values as I do in the below code? I am running on an Intel i7 computer so any options would be appreciated.

#include "stdafx.h"
#include
#include
#include

using namespace std;

class __declspec(align(16)) Element {
public:
Element( float ux, float uy, float uz, float vx, float vy, float vz, float vxold, float vyold, float vzold) {
u.m128_f32[0] = ux;
u.m128_f32[1] = uy;
u.m128_f32[2] = uz;
v.m128_f32[0] = vx;
v.m128_f32[1] = vy;
v.m128_f32[2] = vz;
vold.m128_f32[0] = vxold;
vold.m128_f32[1] = vyold;
vold.m128_f32[2] = vzold;
}

void Move() {
// u = u + (v*1.5 - vold*0.5)*delta_t;
float delta_t = 0.01;
__m128 a, b, c;
a.m128_f32[0] = 1.5;
a.m128_f32[1] = 1.5;
a.m128_f32[2] = 1.5;

b.m128_f32[0] = 0.5;
b.m128_f32[1] = 0.5;
b.m128_f32[2] = 0.5;

c.m128_f32[0] = delta_t;
c.m128_f32[1] = delta_t;
c.m128_f32[2] = delta_t;

u = _mm_add_ps(u, _mm_mul_ps(_mm_sub_ps(_mm_mul_ps(v,a), _mm_mul_ps(vold,b)), c));
}

__m128 u, v, vold;
};

int _tmain(int argc, _TCHAR* argv[])
{
Element A( 1,1,1, 1,2,3, 4,5,6);
A.Move();

cout << A.u.m128_f32[0] << " " << A.u.m128_f32[1] << " " << A.u.m128_f32[2] << endl;

char c;
cin >> c;
return 0;
}

CPU Serial Enable Support on Intel Processor

Wed, 30 Sep 2009 04:07:58 -0700

Hi,
As per the intel documents the CPU Intel III onwards does contain the CPU Serial number.

I have tried most of the things and on multiple PC's could not able to read the serial

with EAX =3 and CPUID instruction on all PCs the CPUID is disabled ie EAX =1 and CPUID

and the EDX 18 the bit is always "0".

Does any body have any Idea how to enable the cpu serial ?