Intel Software Network - feed

PTEST improvement?

Tue, 24 Nov 2009 00:59:42 -0800

Hi,

another benchmark: while I was testing compare performance, the next step is to compare branching on compares, so I wanted to show the impact of ptest in comparison to pmovmskb - cmp. But my results show that ptest is slower in almost all cases. See the first page of compare.pdf for the results. I would understand ptest and pmovmskb showing the same speed if both instructions count as being in the "integer domain", therefore both having the same 1 cycle penalty wrt. domain crossing (is this correct?).

Am I understanding correctly, that in principle ptest and pmovmskb execute equally fast and that the cmp-jump can be optimized via macro-fusion so that both vector-branching implementations really are equivalent (except for the one additional GPR that the pmovmskb version requires)? Where then could the difference come from?

(Yes, I will have to try out the simulator. I did not find the time yet to try it.)

For reference:
(float_v::operator<).isFull():

with ptest:
cmpltps %xmm1,%xmm0
ptest %xmm2,%xmm0
jae
(where xmm2 is 0xfffff...)

without ptest:
cmpltps %xmm1,%xmm0
pmovmskb %xmm0,%ecx
cmp $0xffff,%ecx
je

!(float_v::operator<).isEmpty():

with ptest:
cmpltps %xmm1,%xmm3
ptest %xmm3,%xmm3
je

without ptest:
cmpltps %xmm1,%xmm3
pmovmskb %xmm3,%ecx
test %ecx,%ecx
je

Low rate on sse2 code

Mon, 23 Nov 2009 11:39:47 -0800

Hi!
why this scalar sse2 code (all data in L1 cache) executes on Core2 only on rate 1.49 flop/cycle?

L10:
movsd (%esi), %xmm5
movsd (%ebx), %xmm4
addl $4, %edi
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm3
movsd (%ecx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm2
movsd (%edx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm1
movsd (%eax), %xmm4
mulsd %xmm5, %xmm4
movsd 8(%esi), %xmm5
addsd %xmm4, %xmm0

movsd 448(%ebx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm3
movsd 448(%ecx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm2
movsd 448(%edx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm1
movsd 448(%eax), %xmm4
mulsd %xmm5, %xmm4
movsd 16(%esi), %xmm5
addsd %xmm4, %xmm0

movsd 896(%ebx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm3
movsd 896(%ecx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm2
movsd 896(%edx), %xmm4
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm1
movsd 896(%eax), %xmm4
mulsd %xmm5, %xmm4
movsd 24(%esi), %xmm5
addsd %xmm4, %xmm0

addl $32, %esi
movsd 1344(%ebx), %xmm4
addl $1792, %ebx
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm3
movsd 1344(%ecx), %xmm4
addl $1792, %ecx
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm2
movsd 1344(%edx), %xmm4
addl $1792, %edx
mulsd %xmm5, %xmm4
addsd %xmm4, %xmm1
movsd 1344(%eax), %xmm4
addl $1792, %eax
mulsd %xmm5, %xmm4
cmpl $56, %edi
addsd %xmm4, %xmm0

jne L10

how to rewrite this code for achievement near theoretical peak rate (2.0 flop/cycle)?

How many info could I get to estimate DRAM bandwidth?

Tue, 17 Nov 2009 08:17:55 -0800

I am now working on a work to estimate the active time of DRAM. How could I get info about memory access times by cpu?
Thanks a lot!

Understanding my Benchmarks

Tue, 10 Nov 2009 08:13:08 -0800

Hi,
I wote a benchmark to compare thpossible speedup with SSE vs. scalar execution. But I don't undestand the results I get.
The following loop:
loop:
movaps 0x10(%rax),%xmm1
cmpltps %xmm1,%xmm0
movaps 0x20(%rax),%xmm0
cmpltps %xmm0,%xmm1
movaps 0x30(%rax),%xmm1
cmpltps %xmm1,%xmm0
add $0x40,%rax
movaps (%rax),%xmm0
cmpltps %xmm0,%xmm1
cmp %rax,%rbx
ja loop
appears to require ~2 cycles per movaps+cmpltps (8 cycles per iteration) on a Nehalem processor. (The memory it iterates over is of a size < L1 size.)

The generated code for the scalar case looks like this:
loop:
movss 0x4(%rax),%xmm1
ucomiss %xmm0,%xmm1
seta %dl
movss 0x8(%rax),%xmm0
ucomiss %xmm1,%xmm0
seta %dl
movss 0xc(%rax),%xmm1
ucomiss %xmm0,%xmm1
seta %dl
add $0x10,%rax
movss (%rax),%xmm0
ucomiss %xmm1,%xmm0
seta %dl
cmp %rax,%rbx
ja loop
This requires ~1.33 cycles per ucomiss (i.e. 5.33 cycles per iteration) on the same processor. (Same memory size, too.)

The result is that to compare N floats with SSE I need N/2 cycles. Without SSE I need 1.33*N cycles. That's a speedup of factor 2.66. I expected something closer to a factor of 4 than that...

Now I'm trying to understand where this comes from:
1. the cmpps result is not used, therefore only the throughput should count, i.e. I can execute one cmpps per cycle. Do the movaps account for the second cycle? Could the movaps execute in parallel with cmpps if they'd use a different register?
2. The ucomiss call has a latency of 1 cycle. The result of set is not used, therefore the instruction can run in parallel with everything else. The movss instruction can execute in parallel to the previous ucomiss and seta. So 1.33 looks sensible, but I can't fully understand where this comes from.
Question: Does the second call to seta have to wait for the first one to retire because it writes to the same register?

Anybody that can help me to understand instruction level parallelism better?

help on detecting stalls(identifying structural hazards) in assembly code

Wed, 28 Oct 2009 10:18:15 -0700

Hi All,
Our project is to optimize instruction scheduling in gcc by detecting structural hazards. We are trying to come up with a test case for the same, a scenario wherein one of the instructions is stalled due to the resource being used by some other instruction. However, we are unable to do so.

1. We wrote a C program - doing - floating point multiplications, divisions and additions. However in both the files - 'progname.s' file and 'progname.c.190r.sched2' file, the instructions were scheduled for execution in sequential order. We couldn't find a way to detect a stall, by looking at the assembly code generated.
Question: How do we detect that a stall has occurred if execution is being carried out in a particular sequence?
Also we would like to know of a tool, which given a 'progname.s' file, gives details of the execution time of each instruction and the clock cycle in which stall will occur, if execution is carried out in this sequence.

2. We saw that integer operations were already being performed during compilation. Hence we were left with only floating point operations to be looked into for structural hazards.
Question: Once a stall is detected in case of floating point unit being used currently by some other instruction, which instruction can be scheduled in so as to avoid this stall(since integer operations are performed at compile time and floating point units are being used)?

Target machine architecture: 686
Working on: Intel Pentium Dual Core processor

Thanking you,
Dhiraj

is there a standard format in which we provide architecture specific information to a software

Sun, 25 Oct 2009 16:24:53 -0700

Hi All,
Our project requires us to specify architecture specific information to gcc(not .md files in gcc). We need to specify number of cycles taken per instruction for 686 architecture - as information to gcc.

Question: Is there a standard format in which we define the architecture specific information to softwares requiring these? Do we have the architecture specific information for Pentium Dual Core architecture in a format, that can be read by any software requiring it?

Target Architecture: 686 processor
Working on: Intel Pentium Dual Core processor

Thanking You,
Dhiraj.

how to turn off out-of-order execution in Intel processor

Sun, 25 Oct 2009 14:32:29 -0700

Hi All,
Our project is to optimize instruction scheduling in gcc, by detecting structural hazards. The algorithm employed requires no out-of-order executions by the processor.

Question: Is there a command/mechanism to turn out-of-order execution off in Intel processor?
Target Architecture: 686 processor
Working on: Intel Pentium Dual Core processor

Thanking You,
Dhiraj.

Parallel instructions for detecting MSB in array of bytes

Fri, 16 Oct 2009 01:58:32 -0700

First time posting, not sure if correct forum, but...

I have a large array of bytes, max up to 1600, but mostly up to 128.

Bytes are typically 7-bit of information, and the MSB is used as a sentinel, so the MSB is set in a small portion of the bytes.

Currently I'm looping through them in a loop, but is there a better way to use SSEx to process 128 bytes in parallel and get back a SSE vector with bits set for each byte?

Any suggestions?

Thank you,
craptacus

Why only CS, IP and EFLAGS are saved while interrupt??

Fri, 16 Oct 2009 01:34:34 -0700

I am new to assembly programming. I was reading about 386 Interrupt. I came to know that only CS, IP and EFLAGS are saved as a part of interrupt, they pop back when we have iret. But I am wondering, why they didnt save all the visible registers, segments register etc.,???

Please excuse me, if I understood something wrong.

Thanks for your effort in helping me...

Out of order execution

Thu, 15 Oct 2009 23:53:15 -0700

Is there a simulator and/or a general procedure one can follow to predict what instructions will be executed in what order (assuming all data is in the L1 cache)? I'm having a hard time comprehending why a given instruction sequence executes much faster than another. I suspect it's due to the out of order execution and register renaming, but I've found no tangible reason yet. Any help would be appreciated.