Intel Software Network - <![CDATA[ Opcode semantics ]]> feed http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656 en-us Re: Opcode semantics ]]> http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656/ Sat, 31 Oct 2009 02:28:45 -0700 http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656/ Parallel Programming ISN General Re: Opcode semantics
Quoting - matt.j
Any ideas, anyone?

no idea, but here is the best place I know for this kind of subtleties:

http://www.agner.org/optimize/

]]> http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656/ Sat, 31 Oct 2009 11:23:22 -0700 http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656/ Parallel Programming ISN General Re: Opcode semantics
Quoting - matt.j
Hi,


Firstly, I apologize if this is the wrong forum; I could not find any other more relevant.

I'm looking for clarification in regards to a statement made that asserts there is a 1-cycle difference between the instructions:

0x3B (cmp reg, mem)
0x39 (cmp mem, reg)

As the two are functionally equivalent, I assume it would have to have something to do with the decoding circuit logic, but would like clarification if this statement reigns true in the first place.

Additionally, if this is true, where would I be able to find documentation of such details? All of the manuals I've read (even the IA32 optimization manual) does not mention these things.


Thanks,

Matt.


Just a guess, but normally an instruction with a memory location as the 'destination' operand takes an extra cycle for the write operation. cmp doesn't actually write anything to the destination, but it might simplify the logic to handle these instructions uniformly and skip the write at a later point (where latency might also be less of an issue). Compilers shouldn't emit this anyway, so they can make compromises like these. ]]> http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656/ Mon, 02 Nov 2009 00:38:59 -0800 http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/67656/ Parallel Programming ISN General