Intel Software Network - <![CDATA[ Intel® VTune™ Performance Analyzer ]]> feed http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer en-us Bus transactions and cache miss
Hi,

I've been trying to understand how bus and memory performance counters actually work. My first question is regarding BUS_TRANS_BRD. According to the definition it counts the number of "burst read" transactions, including L1 data cache read misses, L2 hw prefetches and IFU misses. This is not clear enough. Does it count the L1 requests that are missing L2 as well? If that is the case, then why should a multi-threaded program running on two cores that are sharing a L2 cache produce no cache miss (L2_LINES_IN) but a lot of BUS_TRANS_BRDs:
L2_LINES_IN is about 1000,
BUS_TRANS_BRD is about 100 million.

If this counter is only counting L1 data read misses, then why a single threaded program with small data (large enough not to fit in L1, about 100K) is not producing any BUS_TRANS_BRDs?

My second question is about L2_LINES_IN and MEM_LOAD_RETIRED:L2_LINE_MISS. According to definitions L2_LINES_IN counts the number of allocated lines in L2 and L2_LINE_MISS counts the number of loads that missed L2. Based on these definitions L2_LINES_IN must always be greater than L2_LINE_MISS. Because whenever a load is missing the cache, a line must be allocated in L2 cache. However, for my multithreaded application, with two threads sharing a L2 cache, there are no cache misses (L2_LINES_IN) because the data is small and it fits L2, but there are plenty of MEM_LOAD_RETIRED:L2_LINE_MISSes (90 million). How can this be?

The nature of my multithreaded program is to allocated a shared array (an integer array of length 25 (or 40K in another test)), then spawn two threads that try to swap the numbers in this shared array. Before the swapping they lock the data (spinlock, one lock per item in the array) and then they do the swapping.

Thanks!
]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70096/ Mon, 23 Nov 2009 23:27:40 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70096/ ISN General performance counters for intel core i7 Where can I find a good documentation with all the event names and descriptions for core i7 ?
http://www.intel.com/software/products/documentation/vlin/ - this document only has them for core 2 duo (and some others).

thanks ]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70088/ Mon, 23 Nov 2009 14:51:28 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70088/ ISN General What&#39;s goin wrong with this code?
This is the first time I use vTune, to tune a quite complex bit of C-code.
All it does is basically "Calculate x and add it to an unsined char, and clip it to 255", for a lot of pixels.
Because of the complex nature of the code, its hardly possible to optimize it :-/

vTune tells me a lot of time is used for modifying the data itself:


READ/WRITE are bacially pointer-access wrapper macros, clip255 is simple clipping method.

Any ideas why so many cycles are spent here?

Furthermore, is this really the assembler generated for the C code, or does vTune mix things up?
I am only able to read assembler a bit, but clip255 should generate at least some kind of conditional operation like cmov or a compare+jump, but I don't see something like this in the code.

Thank you in advance, Clemens ]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70071/ Sun, 22 Nov 2009 13:59:07 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70071/ ISN General About VTune metrics
I have been using VTune for a while and I would appreciate some advice about the metrics I'm trying to measure (I'm using a processor from Harpertown family - Core microarchitecture):

1) Stall time: Processor's documentation states that it can issue/retire up to 4 instructions per cycle. Assuming that the ideal CPI in this case is 0.25, may I compute the relative stall time as (Measured_CPI-0.25)/Measured_CPI? E.g. Assuming that the measured CPI is 1.25, is it correct to say that the total stall time is 80% (1/1.25)?

2) L2 miss penalty: How correct/accurate is to compute stall time due to L2 misses as: L2_misses * avg_mem_latency? Btw, what is the most precise way to measure average memory latency? I've tried to use the counter "BUS_REQUEST_OUTSTANDING", as suggested in the Intel 64 and IA-32 Optimization Reference Manual, but the results using this counter do not make sense (in some cases, VTune reports BUS_REQUEST_OUTSTANDING events > CPU_CLK_UNHALTED.CORE events)

3) L2 cache miss rate: I was wondering whether the builtin "L2 Cache Miss Rate" ratio afforded by VTune is inconsistent with what most of us consider as "miss rate" (number of misses in L2 divided by number of accesses in L2). Being "L2 Cache Miss Rate" computed  as L2_LINES_IN.SELF.ANY / INST_RETIRED.ANY, shouldn't it be called "miss per instruction"? Is it correct to compute L2 miss rate as:
L2_RQSTS.SELF.ANY.I_STATE / L2_RQSTS.SELF.ANY.MESI ?
]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70064/ Sat, 21 Nov 2009 18:19:02 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70064/ ISN General call graph crash http://software.intel.com/en-us/articles/application-crashes-when-attempting-call-graph-profiling/ article but even after setting instrumentation level for msvcr80d.dll to minimal it still failes. The jit debugger won't start as described in article though. It also raises a warning related to ntdll "Instrumented module name must be identical to original modu..." (can't read further).

I'm on windows 7 and I use Visual Studio 2005.

Is this a known issue? Or I'm just failing on my end?
]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70062/ Sat, 21 Nov 2009 14:25:23 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/70062/ ISN General meet a crash when invoke &#34;modules&#34; and &#34;java&#34; thread used 1365m and 100% CPU CPU is Intel(R) Xeon(R) E5335@2.00GHz *2 (8 cores)
OS is Fedora
Compiler is ICC 11
I want to analyze my app. My app can be analyzed by vTune at former machine, but  met a crash on this server.
The app runs ok on vtune,but when I invoke "modules", always have a crash, and I had to kill the vtune.
I used "top" and found java used 100% cpu and more than 1300M.
at first I think maybe Hyper-Threading problem,but E5335 hasn't Hyper-Threading.
can you give me a hand?
thx a lot

]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69998/ Thu, 19 Nov 2009 06:35:34 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69998/ ISN General Support for more than 128 cores Release notes for VTune 9.1 has a NOTE requesting to contact Intel if the tool will be used on systems with more than 128 cores. Is there a configurable parameter in VTune that needs to be tuned to get support for systems with more than 128 cores? Also is there a maximum limit on the number of cores that will be supported?

Thanks for your time

]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69949/ Tue, 17 Nov 2009 10:33:06 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69949/ ISN General Support for RedHat Enterprise Linux 5.3 I have recently upgraded my compute nodes to RHEL5.3 and I want to know if this is a supported distribution to use Intel VTune Performance Analyzer 9.1. Release notes for 9.1 mentions that RHEL5 is unofficially supported and the call graph feature doesn't work. Is it still the case?

]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69948/ Tue, 17 Nov 2009 10:25:04 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69948/ ISN General Does VTune support OPENmpi based applications?
Thanks for your time. ]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69947/ Tue, 17 Nov 2009 10:20:53 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69947/ ISN General OOO Bursts Stall I was doing cycle accounting with the methodology given be David Levinthal  for core micro architecture.
I observe that my applications are showing 15 - 25 % of OOO Brust. As per the paper OOO is an execution unit stall.

Can you please expain in more detil about OOO brust,  cause of it and how to minimize it?

Thanking you,

Regards,
Dny
]]> http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69911/ Mon, 16 Nov 2009 03:41:57 -0800 http://software.intel.com/en-us/forums/intel-vtune-performance-analyzer/topic/69911/ ISN General