Loading...
You are not logged-in Login/Register





  • Posts   Search Threads
  • matt.jAugust 13, 2009 7:24 PM PDT   
    Opcode semantics
    Hi,


    Firstly, I apologize if this is the wrong forum; I could not find any other more relevant.

    I'm looking for clarification in regards to a statement made that asserts there is a 1-cycle difference between the instructions:

    0x3B (cmp reg, mem)
    0x39 (cmp mem, reg)

    As the two are functionally equivalent, I assume it would have to have something to do with the decoding circuit logic, but would like clarification if this statement reigns true in the first place.

    Additionally, if this is true, where would I be able to find documentation of such details? All of the manuals I've read (even the IA32 optimization manual) does not mention these things.


    Thanks,

    Matt.

    matt.jOctober 31, 2009 3:28 AM PDT
    Rate
     
    		 #1
    Re: Opcode semantics
    Any ideas, anyone?


    bronxzvOctober 31, 2009 3:53 AM PDT
    Rate
     
    		 #2 Reply To #1
    Re: Opcode semantics
    Quoting - matt.j
    Any ideas, anyone?

    no idea, but here is the best place I know for this kind of subtleties:

    http://www.agner.org/optimize/



    c0d1f1edNovember 2, 2009 12:38 AM PST
    Rate
     
    		 #3
    Re: Opcode semantics
    Quoting - matt.j
    Hi,


    Firstly, I apologize if this is the wrong forum; I could not find any other more relevant.

    I'm looking for clarification in regards to a statement made that asserts there is a 1-cycle difference between the instructions:

    0x3B (cmp reg, mem)
    0x39 (cmp mem, reg)

    As the two are functionally equivalent, I assume it would have to have something to do with the decoding circuit logic, but would like clarification if this statement reigns true in the first place.

    Additionally, if this is true, where would I be able to find documentation of such details? All of the manuals I've read (even the IA32 optimization manual) does not mention these things.


    Thanks,

    Matt.


    Just a guess, but normally an instruction with a memory location as the 'destination' operand takes an extra cycle for the write operation. cmp doesn't actually write anything to the destination, but it might simplify the logic to handle these instructions uniformly and skip the write at a later point (where latency might also be less of an issue). Compilers shouldn't emit this anyway, so they can make compromises like these.

Forum jump:  

Intel Software Network Forums Statistics

16,376 users have contributed to 46,361 threads and 164,026 posts to date.

In the past 24 hours, we have 13 new thread(s) 30 new posts(s), and 25 new user(s).

In the past 3 days, the most popular thread for everyone has been Program compiles in release but not debug The most posts were made to Take a look at John Burkhard&# The post with the most views is vectorization of sin/cos results in wrong values

Please welcome our newest member brownwatch75


For more complete information about compiler optimizations, see our Optimization Notice.