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Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
 
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Topic / Topic starter Post date Repliessort ascending Last post
Normal topic RAPL for energy measurement
by Yunqi Z. » Wed, 04/03/2013 - 13:52 		Wed, 04/03/2013 - 13:52 8
 by iliyapolak
Sun, 04/07/2013 - 01:11
Normal topic RAPL, DRAM and PCM
by Jee C. » Mon, 11/05/2012 - 13:00 		Mon, 11/05/2012 - 13:00 8
 by iliyapolak
Mon, 12/31/2012 - 23:15
Normal topic Global Variables with ifort
by Rafael Silva » Mon, 09/17/2012 - 06:45 		Mon, 09/17/2012 - 06:45 7
 by Rafael Silva
Wed, 09/19/2012 - 05:01
Normal topic Xeon E5 L3 cache is organized how?
by Zack -. » Tue, 10/30/2012 - 09:26 		Tue, 10/30/2012 - 09:26 7
 by andres-more (Intel)
Mon, 11/05/2012 - 05:00
Normal topic Odd cache results
by korso » Wed, 06/20/2012 - 05:52 		Wed, 06/20/2012 - 05:52 7
 by Sanath Jayasena
Fri, 06/29/2012 - 13:55
Normal topic Avoid cache writing on read?
by yotamhc » Tue, 11/29/2011 - 05:36 		Tue, 11/29/2011 - 05:36 7
 by Sergey Kostrov
Tue, 11/29/2011 - 05:36
Normal topic Amazing but unexpected behavior of a simple C language test
by bostoniancarlos » Thu, 03/22/2012 - 15:29 		Thu, 03/22/2012 - 15:29 7
 by Sergey Kostrov
Thu, 03/22/2012 - 15:29
Normal topic Windows WMI Win32_CacheMemory class - cache Associativity values
by nrcaliendo » Mon, 06/25/2012 - 05:42 		Mon, 06/25/2012 - 05:42 7
 by Sergey Kostrov
Thu, 06/28/2012 - 18:07
Normal topic Sandybridge processors report incorrect core number?
by Liam McSherry » Sat, 12/29/2012 - 10:42 		Sat, 12/29/2012 - 10:42 7
 by Liam McSherry
Sat, 12/29/2012 - 14:28
Normal topic Unusual Pointer Chasing Memory Latency on SLES 11 SP2 with E5-2670
by perfwise » Thu, 05/10/2012 - 13:33 		Thu, 05/10/2012 - 13:33 7
 by Patrick Fay (Intel)
Wed, 05/30/2012 - 11:15
Normal topic Performance of C++ 2D array iterator dereferencing
by tj1 » Fri, 06/29/2012 - 09:49 		Fri, 06/29/2012 - 09:49 7
 by Sergey Kostrov
Fri, 07/06/2012 - 17:20
Normal topic Memory bound characterization on Ivy Bridge
by Yunqi Z. » Mon, 03/04/2013 - 14:56 		Mon, 03/04/2013 - 14:56 7
 by perfwise
Wed, 03/06/2013 - 04:45
Normal topic Description of DRAM Refresh Unit Masks?
by Nash R. » Wed, 02/13/2013 - 09:17 		Wed, 02/13/2013 - 09:17 7
 by iliyapolak
Thu, 02/14/2013 - 22:28
Normal topic Trying to disable Processor idle states (C states) on Windows PC
by mashdev » Mon, 03/26/2012 - 13:56 		Mon, 03/26/2012 - 13:56 7
 by iliyapolak
Sat, 12/22/2012 - 00:54
Normal topic Vtune Strange Counters
by Rafael Silva » Thu, 06/28/2012 - 14:40 		Thu, 06/28/2012 - 14:40 7
 by Rafael Silva
Sat, 06/30/2012 - 15:34
Normal topic Intel PCM - What does nominal CPU mean of?
by GHui » Mon, 02/06/2012 - 23:57 		Mon, 02/06/2012 - 23:57 7
 by bobjc
Thu, 02/16/2012 - 03:35
Normal topic Write Combining Buffer
by Srinath Sridharan » Tue, 05/15/2012 - 16:44 		Tue, 05/15/2012 - 16:44 7
 by Igor Levicki
Sat, 05/19/2012 - 05:30
Normal topic Passing some memory boundary values to 'prefetcht*' instructions
by Sergey Kostrov » Fri, 12/23/2011 - 06:04 		Fri, 12/23/2011 - 06:04 6
 by k_sarnath
Fri, 12/23/2011 - 06:04
Normal topic Memory store retirenment
by Wang Jaff » Sun, 07/15/2012 - 09:28 		Sun, 07/15/2012 - 09:28 6
 by Hussam Mousa (Intel)
Mon, 08/13/2012 - 09:04
Normal topic Can't use PCM
by korso » Thu, 06/14/2012 - 08:17 		Thu, 06/14/2012 - 08:17 6
 by Roman Dementiev...
Thu, 10/04/2012 - 05:40
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For more complete information about compiler optimizations, see our Optimization Notice.