http://stackoverflow.com/questions/784041/how-do-i-programatically-disable-hardware-prefetchinggives you advice on where to look in linux kernel and /dev/ for hardware prefetch settings.
http://software.intel.com/en-us/articles/optimizing-application-performance-on-intel-coret-microarchitecture-using-hardware-implemented-prefetchers/ shows a setup screen for a BIOS which includes these settings (seen on only a few servers)
Tinkering with these settings seems to be much less popular than it was several years ago, judging by the reduced number of Google hits.
When you say Core 2, I don't think you mean the Xeon 7xxx 4-socket servers with L3 cache, a special case where disabling hardware prefetch might have produced performance gains, perhaps 5%, on certain job types, and, of course, much large losses on others.
The adjacent sector (cache line pairing) might more often reduce performance, particularly where threads operate about 1 cache line apart, with one reading and the other writing data. Perhaps people have learned to improve their threading rather than trying to patch up these situations by disabling prefetch.
