How to separately control MSRs on Intel Core 2

zhangyihere
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100
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Green Belt
November 3, 2009 5:30 PM PST
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#2
Thanks for the fast reply! But in some literature, I have read that all cache prefetchers on their platform are percore
configurable except the L2 adjacent line prefetcher. The platform they use is Intel Xeon 5160. 

Could you give me some further advice on how to implement such functions?

Thanks

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