Let some instruction "INSTR reg,reg" have latency Lr and throughput Tr
and let cache memory have latency Lm and throughput Tm
how to calculate latency and throughput of instruction "INSTR mem,reg"?
Simply add Lr+Lm and Tr+Tm?
yes, you need to sum the latencies, but take the _minimum_ of the two throughputsin the case of e.g. ALU operation and memory operation, since they don't share execution ports, but it may be different for other operations/instructions chains. Plus, if your instruction is a vector integer one (e.g. SSE2) you need to add 1 cycle of inter-stack bypass latency between load and operation, add 2 cycles in the case offloatingpointoperation for Nehalem processor.
-Max
-Max
"INSTR mem,reg" uses two ports?
how to calculate throughput, if there is no free port for memory operation?