I am writing a benchmark on my Core i7 sandybridge platform. In which I want to test DRAM by using uncacheable memory(setting a range of pages uncacheable).
To what i know, normally, DRAM bursts data to up layers. But if there is uncacheable memory, does DRAM still work in burst mode? If still in burst mode, does data be stored in somewhere? Or, on cacheable memory, data is sent by single word or byte between core and DRAM.
And, for uncacheable memory, the page tables can still be buffered in TLB, right?