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    <title>Intel Software Network - <![CDATA[ Virtualization & Software Development ]]> feed</title>
    <link>http://software.intel.com/en-us/forums/virtualization-software-development</link>
    <description></description>
    <language>en-us</language>
    <item>
      <title>Nice tip !</title>
      <description><![CDATA[ Nice tip! Thanks a lot for this one.  <br />http://www.topfloristperu.com ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/70084/</link>
      <pubDate>Mon, 23 Nov 2009 09:43:23 -0800</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/70084/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>VMFailInvalid returned by VMXON</title>
      <description><![CDATA[ <p>Hello,<br /><br />I am trying to use VMX on a 2xCPU Intel(R) Xeon(R) 5130 @ 2.00GHz machine. After I issue the VMXON instruction, I find that CF is set, which I understand is the indication of a VMfailInvalid result [1]. Here are the setup steps I have taken:<br /><br />I have verified that the CPU supports VMX by checking ECX.VMX after issuing CPUID.1;<br />I have checked that CR4.VMXE is cleared (i.e., nothing else has entered VMX operation);<br />I have set CR4.VMXE;<br />I have checked that CR0 and CR4 comply with the IA32_VMX_CR*_FIXED* MSRs<br />I have read size from IA32_VMX_BASIC[bits 44:32] (On my system, 2048 bytes)<br />I have secured the required 2048 bytes of page-aligned memory (e.g., starting at 0xd0519000)<br />I have written revid from IA32_VMX_BASIC[bits 31:0] to my VMXON region<br />I have passed the physical address of my VMXON region to the VMXON instruction<br /><br />I don't know how to check, but based on the what I have read about A20M#, I highly doubt it is a factor--is that a good assumption?  I wonder if I am correctly passing in the m64 operand of the VMXON instruction using gcc inline assembly.  Can someone provide an example of the correct inline assembly for this? Or, better yet, tell me something I am doing wrong?  My source code (compiles and loads in Linux 2.6.18, 2.6.22) and kernel log output are attached in a ZIP file.  The output is duplicated below for ease of diagnosis.<br /><br />Thanks..<br />        -M.<br /><br />Footnotes:<br />1. Developer's Manual vol. 2B, sec. 5.2 - Conventions<br /><br />Output:<br />VMX capable<br />Feature control checks<br />IA32_FEATURE_CONTROL.lock[bit 0] = 1: yes<br />IA32_FEATURE_CONTROL.VMXINSMX[bit 1] = 0<br />IA32_FEATURE_CONTROL.VMXOUTSIDESMX[bit 2] = 1: yes<br />Linux KVM check: IA32_FEATURE_CONTROL &amp; 5 == 5<br />CR4.VMXE set successfully<br />CR0 checks:<br />CR0.NE = 1: yes<br />CR0.PE = 1: yes<br />CR0.PG = 1: yes<br />CR0 valid for VMXON<br />CR4 checks:<br />CR4.SMXE = 0: yes<br />CR4.VMXE = 1: yes<br />CR4 valid for VMXON<br />Other conditions worth noting:<br />CR4.PAE = 0<br />IA32_VMX_BASIC.REVID[bits 31:0] = 0xb (11)<br />IA32_VMX_BASIC.VMXONBYTES[bits 44:32] = 2048 bytes<br />IA32_VMX_BASIC.WIDTH32[bit 48] = 0<br />VMXON region address width limited only to the physical address width<br />Physical address width: 38 bits<br />Preparing VMXON region<br />vmxon_region = 0xee96f000<br />vmxon_pa = 0x00 0xf0 0x96 0x2e 0x00 0x00 0x00 0x00 <br />VMXON returned VMFailInvalid</p> ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69932/</link>
      <pubDate>Mon, 16 Nov 2009 22:43:51 -0800</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69932/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Kernel diver for virtualization?</title>
      <description><![CDATA[ Hello,<br /><br />I've been reading up on the Intel-VT and the VMX instructions, but it seems that in order to get the CPU into a VMX-ready state I need to modify the CR4 register, which can only be done from within the kernel (at least under Windows). My problem is that I would like to write a dead-simple driver that only turned on the VMX operations and maybe did some minor housekeeping, yet to install this drvier under 64bit Windows I need to digitally sign the driver... which would cost hundreds of dollars. Why do I need kernel access in order to be able to write a small hypervisor for my project? As a university student I have absolutely no means of paying for the required certificates from VeriSign or whatever.<br /><br />How is this issue solved with other projects? Does every single project that use Intel-VT pay for special certificates and such, or am I missing something? Is a pricey certificate needed for every single open source project that would like to use virtualization one way or the other?<br /><br />Have a nice day,<br /> Peter ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69876/</link>
      <pubDate>Fri, 13 Nov 2009 08:11:55 -0800</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69876/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Could intel somehow initiate migration/cleanup for x86 instruction set?</title>
      <description><![CDATA[ I don't like x86 instruction set because it is full of exceptions and arbitrary historical conventions. On top of this every new group of instructions follows the suit. It's not CISC anymore, more like OCISC standing for 'Over-Complicated Instruction Set Computer'.<br /><br />I'm writing <a href="http://bitbucket.org/cheery/g386/">a quite nice x86 assembler in python</a> to get a backend for compiler I'm working on. The trouble is that it is probably impossible for me to use anything except the smallest subset of x86 if I want to keep it simple and easy to read. This far I think I've done somewhat well as long as I carefully read the instruction set reference to avoid all the possible oddities I might locate.<br /><br />Partially I'm frustrated because x86 has forced me through thick swamp to actually be able of doing anything like this. It's not completely bad thing since I've learned to treat superfluous complexity through avoidance. Mostly it is an annoyance and is able of complicating whatever code generator library one needs to implement for the platform.<br /><br />Could hardware designers at intel provide an alternative aside x86-instruction set? Requirements would be that writing an assembler/code generator for it must be simple, and it must reach performance greater or alike to the x86 machine code. It could be also possible to achieve this by just picking up a collection of instructions that are easy to deal with.<br /><br />As I've attempted to write an assembler, I've figured there's couple of changes into instruction set that could make it considerably easier to implement code generators. Fixed instruction length is one of them. Simple thing as encoding instruction length&amp;arguments into varying-width opcode and getting rid of modrm/sib/address size -bytes would already do it lot easier for writing instruction encoders.<br /><br />There's also one very sneaky thing you could do, ok. Here's how it'd go: Write a manual that describes 50-100 instruction forms that, when implemented would allow writing as efficient programs as before. Promote compilers, assemblers and software that are using this new suspended instruction set. Then, one pretty day, release a new architecture that contains this subset and completely new instruction set, but contains software emulation layer for the whole messy history of the x86.<br /><br />The idea in this approach lies behind the fact that the computing power increases exponentially every three years. Introduce and force the restricted instruction set for couple of years for the newly written software. In this time the current software stop being latest edge in hogging computing performance and emulating them will provide sufficient performance for anyone still using them. ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69862/</link>
      <pubDate>Thu, 12 Nov 2009 16:16:51 -0800</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69862/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Could intel somehow initiate migration/cleanup for x86 instruction set?</title>
      <description><![CDATA[ I don't like x86 instruction set because it is full of exceptions and arbitrary historical conventions. On top of this every new group of instructions follows the suit. It's not CISC anymore, more like OCISC standing for 'Over-Complicated Instruction Set Computer'.
<div><br /></div>
<div>I'm writing <a href="http://bitbucket.org/cheery/g386/">a quite nice x86 assembler in python</a> to get a backend for compiler I'm working on. The trouble is that it is probably impossible for me to use anything except the smallest subset of x86 if I want to keep it simple and easy to read. This far I think I've done somewhat well as long as I carefully read the instruction set reference to avoid all the possible oddities I might locate.</div>
<div><br /></div>
<div>Partially I'm frustrated because x86 has forced me through thick swamp to actually be able of doing anything like this. It's not completely bad thing since I've learned to treat superfluous complexity through avoidance. Mostly it is an annoyance and is able of complicating whatever code generator library one needs to implement for the platform.</div>
<div><br /></div>
<div>Could hardware designers at intel provide an alternative aside x86-instruction set? Requirements would be that writing an assembler/code generator for it must be simple, and it must reach performance greater or alike to the x86 machine code. It could be also possible to achieve this by just picking up a collection of instructions that are easy to deal with.</div>
<div><br /></div>
<div>As I've attempted to write an assembler, I've figured there's couple of changes into instruction set that could make it considerably easier to implement code generators. Fixed instruction length is one of them. Simple thing as encoding instruction length&amp;arguments into varying-width opcode and getting rid of modrm/sib/address size -bytes would already do it lot easier for writing instruction encoders.</div>
<div><br /></div>
<div>There's also one very sneaky thing you could do, ok. Here's how it'd go: Write a manual that describes 50-100 instruction forms that, when implemented would allow writing as efficient programs as before. Promote compilers, assemblers and software that are using this new suspended instruction set. Then, one pretty day, release a new architecture that contains this subset and completely new instruction set, but contains software emulation layer for the whole messy history of the x86.</div>
<div><br /></div>
<div>The idea in this approach lies behind the fact that the computing power increases exponentially every three years. Introduce and force the restricted instruction set for couple of years for the newly written software. In this time the current software stop being latest edge in hogging computing performance and emulating them will provide sufficient performance for anyone still using them.</div> ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69861/</link>
      <pubDate>Thu, 12 Nov 2009 16:13:37 -0800</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69861/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Redirecting host interrupts to the guest</title>
      <description><![CDATA[ I am implementing thin hypervisor which runs under primary OS which is executed as guest. To implement such things as shadow paging I need hardware interrupts to be enabled in the host. I am trying to set a coresponding bit in the bitmap for each hardware interrupt delivered through the host IDT. On VM entry I am injecting to the guest all interrupts which have happened during VM exit processing and have corresponding bits set in the bitmap. Interrupts with higher priorities are injected first. <br /><br />Everything works fine, but sometimes (very rarely) guest hangs without VM exits committed.<br /><br />Question to experts: is this design right and what could be a reason for the hang?<br /> ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69553/</link>
      <pubDate>Sat, 31 Oct 2009 19:21:28 -0700</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69553/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Any CPU with both EPT and TXT support?</title>
      <description><![CDATA[ I'm wondering whether there is a processor that supports both EPT and TXT because I wanna build an efficient VMM with measurement.<br /><br />Thanks. ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69500/</link>
      <pubDate>Thu, 29 Oct 2009 02:06:56 -0700</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69500/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Q8400 + DG31PR Virtualization Support</title>
      <description><![CDATA[ The Q8400 processor has VT built-in. The DG31PR motherboard has VT enabled in the bios.<br /><br />But when I "cat /proc/cpuinfo" no vmx flag shows up.<br /><br />??? ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/69466/</link>
      <pubDate>Wed, 28 Oct 2009 06:57:21 -0700</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/69466/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>values of genral purpose registers </title>
      <description><![CDATA[ hi my friends<br />when transitioning from a VM to the VMM, where are values of genral purpose registers  stored ?<br />sincerely u ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/68920/</link>
      <pubDate>Thu, 08 Oct 2009 08:11:06 -0700</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/68920/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
    </item>
    <item>
      <title>Question about sysenter/sysexit</title>
      <description><![CDATA[ Hi; in (<a target="_blank" href="http://www.intel.com/technology/itj/2006/v10i3/1-hardware/3-software.htm">http://www.intel.com/technology/itj/...3-software.htm</a> ) it's declared that <br />Executions of SYSENTER by a guest application cause transitions to the VMM and not to the guest OS. The VMM must emulate every guest execution of SYSENTER.<br />It means that execution of sysenter instruction cause a VM Exit and transfer control to VMM to handle guest's system calls. Please say me how VMM handles guest's system calls? <br />Dose VMM uses guest system calls handler routines to handle guest's system calls?<br /> ]]></description>
      <link>http://software.intel.com/en-us/forums/virtualization-software-development/topic/68917/</link>
      <pubDate>Thu, 08 Oct 2009 07:51:36 -0700</pubDate>
      <guid isPermaLink="true">http://software.intel.com/en-us/forums/virtualization-software-development/topic/68917/</guid>
      <category>Virtualization</category>
      <category>ISN General</category>
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