AES New Instructions
- Intel® AES New Instructions (Intel® AES-NI)
Overview of Intel® AES-NI, a new encryption instruction set that improves on the Advanced Encryption Standard (AES) algorithm and accelerates the encryption of data.
- Securing the Enterprise with Intel® AES-NI
Learn why cryptography is hot in the marketplace today, especially in the enterprise.
- Intel® Advanced Encryption Standard Instructions (AES-NI)
Description of the six new instructions that make up the AES-NI instruction set and perform several compute intensive parts of the AES algorithm.
Digital Random Number Generator
- Bull Mountain is Intel's code name for its new Intel® 64 Architecture instruction RdRand and its underlying Digital Random Number Generator (DRNG) hardware implementation. Bull Mountain provides a processor-based RNG solution that is of high quality and performance, highly available, and secure.
Intel Instruction Set Architecture Extensions
- Intel® Memory Protection Extensions (Intel® MPX) is a name for Intel Architecture extensions designed to increase robustness of software
- Software Guard Extensions (SGX) is a name for Intel Architecture extensions designed to increase the security of software through an “inverse sandbox” mechanism
- Intel® Secure Hash Algorithm Extensions (Intel® SHA) are a family of seven Intel® Streaming SIMD Extensions (Intel® SSE)-based instructions that are used together to accelerate the performance of SHA-1 and SHA-256 on Intel architecture-based processors
Intel® Virtualization Technology (Intel® VT)
- Virtualization HW technical brief
Intel Virtualization Technology (Intel VT) provides comprehensive hardware assists that boost virtualization software performance, improve application response times and provide greater reliability, security and flexibility.
- Virtualization: A Developer's Friend
The more developers use virtualization, the more they find new uses for it. Discover what you’re missing and how virtualization can help you get more done.
- Intel® Virtualization Technology: Flash* Animation
This animation provides an overview of Intel® Virtualization Technology, which is a technique by which hardware resources can be abstracted, divided, and shared between multiple operating system environments running simultaneously.
- Intel® Virtualization Technology: Best Practices for Software Vendors
This series of articles functions as an aid to help software vendors tailor their applications for use with Intel VT.
By AdminPosted 07/03/201251
Last Updated April 19, 2013 The Intel Hardware Accelerated Execution Manager (Intel® HAXM) is a hardware-assisted virtualization engine (hypervisor) that uses Intel Virtualization Technology (Intel® VT) to speed up Android app emulation on a host machine. In combination with Android x86 emulator ...
By Deleted userPosted 03/05/20120
By Thomas Burger Introduction Virtualization technology is possibly the single most important issue in IT and has started a top to bottom overhaul of the computing industry. The growing awareness of the advantages provided by virtualization technology is brought about by economic factors of scar...
Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices
By TW BurgerPosted 03/05/201210
Virtualization solutions allow multiple operating systems and applications to run in independent partitions all on a single computer. Using virtualization capabilities, one physical computer system can function as multiple "virtual" systems. Intel® Virtualization Technology (Intel VT) improves th...
By robert-mueller-albrecht (Intel)Posted 02/09/20120
Robert Mueller showcases the VTune™ Performance Analyzer usage model for remote data collection on MIDs
By Audri PhillipsPosted 02/19/20130
This is the second blog I have written in which TouchDesigner is mentioned, but this time I have an informative interview with Jarrett Smith, system architect of TouchDesigner and Ben Voigt, product manager of TouchDesigner included. TouchDesigner is a very exciting and unique program. I have a ...
By ylian-saint-hilaire (Intel)Posted 09/18/20122
Last week I was at the Intel Developer Forum and I met up with Jason who works for the Intel AppUp® for Small Business program. I have known him for a long time and I wanted to highlight this program because, for one, they use a lot of the Meshcentral.com technology. As I understand it, and I am...
By James Reinders (Intel)Posted 09/16/20120
One of the great features in Intel® VTune™ Amplifier is the use of the event monitoring registers built into Intel processors. These can give us important insights into what is really happening on a system. The event monitoring allows the profiling of code in terms of what causes caches misses, u...
By Jeff Kataoka (Intel)Posted 02/16/20122
Virtualization of PC's is being used more and more in many companies to help them to maximize their PC resources for a variety of application uses. Some businesses are using virtualization with client PCs with Intel®vPro™ technology and Intel® Active Management Technology (Intel® AMT). Yet, the...
By Penny Svenkeson1
Hi all, In our hypervisor implementation, we can have multiple cores assigned to a single VM. In the multi-core VM configuration, we are seeing longer delays under virtualization for cores getting locks (even when there is no contention for the lock cell). If a core (or thread) has a guest cache line resident and takes a VMEXIT for some reason and another core want to get ownership of the guest cache line (for atomic operation), does the 2nd core have to wait for the VMRESUME on the first core before getting ownership? Are there any other reasons that would prevent a core from completing an atomic operation if other cores are in a VMEXIT condition? Core1 has cache line A Core1 takes a VMEXIT for timer interrupt Core2 tries a sync_fetch_and_add to cache line A <-- get ownership here Core1 does a VMRESUME <-- or wait till here for ownership Thanks for any insight. Penny
Not sure what forum would be most appropriate for this question, but this seemed close at least....kindly advise if there's a better place! For many years my company has been interested in the availability of cross compilation for Windows from Linux. Our primary development environment is Linux, and the various approaches to getting linux buildable software to build on windows involve various levels of pain and suffering of one sort or another. Being able to create native windows binaries without having to duplicate development environments would be a real benefit. Some level of capability in this regard has been available via the MinGW tools for at least a decade, and we used it for a time, but limitations such as inability to debug with ordinary windows tools were too much of a hinderance. Since we believe the claim that ICC is really the same compiler on Windows and Linux, it seems like it would be very straight-forward to create a Linux version of the compiler able to cr...
By Yogi D.1
I am writing a thin hypervisor that allows 16-bit mode guests. The system boots into my 16-bit boot code which sets up 32-bit protected mode with identty mapped pages, then enables IA-32e compatibility mode and then switches into IA32e mode (64-bit). In this mode, the software sets up a hypervisor to allow unrestricted guests (this includes setting up EPT with proper caching controls refecting the cache setup via MTRRs). Then the software launches a 16-bit guest that runs well -- making BIOS calls for I/O services etc. All this is working quite well. However, I noticed a small discrepency in behavior when I press the power button. Before the 16-bit guest is launched, the system immediately shuts down when the power button is pushed. This also happens when the host mode is active (i.e., my code is processing a VM Exit). However, when the 16-bit mode guest is active, pushing the power button causes the machine to hang -- even the VM preemption timer does not cause a VM Exit. Be...
By Tommy F.1
Hello can someone explain why intel vt-d is required for HVM ( fully virtualized VM) and not for Para-virtualized VMs. I know that in the pci-passthrough, the VM has control of the PCI. so the PCI needs to do DMA access to the VM memory, but as this is not possible, the PCI will tell the IOMMU about the virtual address, which will be converted to the physcial address in RAM, which corresponds to the VM memory. But what happens in case of Para-virtualization VM?
By Yogi D.1
Hi. I am writing a small OS-agnostic hypervisor as a teaching tool for my students. The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots. The hypervisor code switches to 32-bit proceted mode and then IA32e (64-bit mode, paged with identity mapping of linear -- physical addresses). It then sets up the 64-bit exception handling mechanism and tests of this exception handling mechanism are successful (CPL and DPL are 0 so no stack switching is expected). E.g., divide by 0, and page faults are handled as expected. Next, an IA32e mode guest is launched. The guest has its own paging tables (these are not identity mapped). The guest handles exceptions and interrutps by itself (i.e., it has a different IDT than the host, and the exception bitmap control is set to 0). All this is working. External interrupts, exceptions, memory accesses, access to I/O devices is working well int he guest. The guest exits to the host because of va...
By David K.0
With the help of Virtual Services, we can start of the software development life cycle. But I have one question in mind can we follow in all Development like Custom, Website and Mobile Application Development?
I am looking for some information on what processor supports new virtualization features. Specifically, I am interested in the following features: The numbers in paranthesis denote the bit position in the secondary processor execution controls - 1. EPT-violation #VE (18) 2. VMCS shadowing (14) 3. Enable VM functions (13) 4. Virtual interrupt delivery (9) 5. Apic register virtualization (8) I have a sandybridge (cpuid leaf1 returns family 0x6, model 0xa, stepping id 0x7) and it does not support the above features. Does anyone know of a current/future cpu that supports these features? Any help is appreciated. Thank you.