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Intel® Xeon® processors provide:

  • Up to 32 cores per system, allowing you to increase performance by threading your code and using pre-threaded libraries
  • Intel® AVX, delivering up to 2X performance in floating point-intensive applications such as financial, scientific, and media
  • Intel® AES-NI instruction-set calls to accelerate data encryption in media, security, and data center applications
  • Intel® Node Manager and Intel® Data Center Manager that let you implement your app so IT managers can better control power usage

Intel Guide for Developing Multithreaded Applications
Develop efficient multithreaded applications to improve multithreading performance.

Intel® Advanced Encryption Standard Instructions (AES-NI)
Learn about the six new instructions for fast and secure data encryption.

Using AVX Without Writing AVX Code
Options to more easily integrate Intel® AVX into your applications.

Intel® Node Manager Programmer's Reference Kit
Server management technology to monitor and control power and thermal behaviors.

Videos

Deliver top application performance while minimizing development, tuning and testing time and effort.

A Concise Guide to Parallel Programming Tools for Intel® Xeon® Processors
Pick the right programming models and tools to boost your application’s performance.

Download Intel® OpenCL SDK
The first open, royalty-free standard for general-purpose parallel programming.

Parallel Studio XE 2013 is here
Powerful tools to make the most of clusters and supercomputers.

Intel® Compiler Options for Intel® SSE and Intel® AVX
Learn about the three main types of processor-specific optimizations.

Optimize, parallelize, and vectorize your code today.

Planning for Parallel Optimization
Get started with an action plan for big performance improvements.

Testing Parallel Programs
Introduction to the parallel software testing methodologies.

Intel® Hyper-Threading Technology: Your Questions Answered
Learn about this performance feature on Intel® Core™ i7 processors and Xeon® 5500 series processors.

Avoiding AVX-SSE Transition Penalties
How to avoid issues when using Intel® AVX.

Intel® 64 Architecture Processor Topology Enumeration
Algorithm for single-socket to multiple-socket platforms using Intel 64 and IA-32 processors.

Intel® Performance Counter Monitor - A better way to measure CPU utilization
Sample C++ routines and utilities to help gain a significant performance boost.

Intel® Advanced Encryption Standard (AES) Instructions Set - Rev 3.01
Instructions that enable fast and secure data encryption and decryption.

Learn more about platforms that support Data Center, Cloud, and High Performance Computing

High Performance Computing (HPC)
New HPC solutions from Intel deliver intelligent performance to meet today's most complex HPC challenges.

Data Center Design for Cloud Computing
Discover Intel’s vision for the future of cloud computing, as well as the technologies that can make it a reality.

Intel® Xeon® Processors
Intel servers deliver enhanced, energy-efficient performance for data-intensive business applications.

Intel® Cluster Ready
Put more power behind your high-performance computing (HPC) applications.
29-Mar-2013
11:26 AM PDT
Is the Intel® Xeon Phi™ coprocessor right for me?
By Eric Gardner (Intel)0
Download Article Download Is the Intel® Xeon Phi™ coprocessor right for me? [PDF 383KB] If you are reading  this article, you likely want to find out more about the Intel® Xeon Phi™ coprocessor and what . . .
29-Mar-2013
10:31 AM PDT
Migrating Server Workloads to Red Hat Enterprise Virtualization on Intel® Xeon® Processor 2600-based Servers for Performance and Cost Improvements
By ROBERT M.0
Continued enhancements to Intel platforms and KVM-based Red Hat Enterprise Virtualization make platform refresh an attractive proposition. Independent testing commissioned by Intel and Red Hat demonstrates that open virtualization on refreshed servers, servers 2 years old or more, enables . . .
28-Mar-2013
3:02 PM PDT
Differences in Floating-Point Arithmetic Between Intel® Xeon® Processors and the Intel® Xeon Phi™ Coprocessor
By Martyn Corden (...0
Download Article Download Differences in Floating-Point Arithmetic Between Intel® Xeon® Processors and the Intel® Xeon Phi™ Coprocessor . . .
26-Mar-2013
9:27 AM PDT
The Importance of Vectorization for Intel® Many Integrated Core Architecture (Intel® MIC Architecture) (Fortran Example)
By Martyn Corden (...0
Reference Link and Download Intel Vectorization ToolsCode tarball [TAR 16KB] Introduction To get good performance out of the Intel® Many . . .

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Intel® Vtune™: “Error connecting to MIC card”, Why?
By Sumedh Naik (Intel)Posted March 29th 20131
Recently, while profiling a workload on the Intel® Xeon Phi™ coprocessor using Intel Vtune, I ran across the following error: Quote: ERROR connecting to MIC card, make sure sep_mic_server is running on the card, retrying connection… ERROR connection to MIC card <1:1046>, errno 111   Before ...
Behind the Scenes: Offload Memory Management on the Intel® Xeon Phi™ coprocessor
By Sumedh Naik (Intel)Posted March 27th 20130
For a lot of people out there, offload is a mysterious construct that by magic switches context to the Intel Xeon Phi coprocessor and makes the code run on the coprocessor without getting the developer’s hands dirty. Although this black box approach is an excellent idea for most part, the ...
Intel® Xeon Phi™ coprocessor Power Management Pt 0: Introduction and inquiring minds
By Taylor Kidd (Intel)Posted March 24th 20130
So exactly which power states exist on the Intel® Xeon Phi™ coprocessor? What happens in each of the power states? Inquiring minds want to know. And since you are, no doubt, aggressively involved in high performance computing (HPC), I am sure you want to know also. This is not going to be a high ...
The Intel® Xeon Phi™ coprocessor: What is it and why should I care? Pt 1: Fitting it all on one slab of silicon
By Taylor Kidd (Intel)Posted March 22nd 20132
Hi, my name is Taylor Kidd. You many know me from such notables as, “The Beginning Intel® Xeon Phi™ Coprocessor Workshop,” and, “The Advanced Intel® Xeon Phi™ Coprocessor Workshop ...

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Marco S.Thu, May 9th 2013 - 12:50
Need single thread dll in fortran5
Hi,sorry i am a mathematician who can more or less program, so, please, forgive my low level question. I am building a 32bit dll with intel fortran 2013 from visual studio 2010 on windows.I need to call it from R ( a statistical program). which requires very simple single thread dlls (obviously no ...
zalia64Tue, May 7th 2013 - 22:41
64-bit bug in Visual C++? mov R8d,imm not completley defined12
The Intel  documentation does not specify wether  mov R8d , -1  will also zero the high dword of R8, or leave it intact.  The Microsoft Visual C++  (2010)  translate the C line  a = myfunc(par1, par2, 3) ; into          mov RCX, par1 ; mov RDX, par2 ;   mov R8b, 3 ;    call myfunc;    move qword ...
maratyszczaWed, May 1st 2013 - 16:06
Haswell RCPPS/RSQRTPS implementation16
Hi, I work on code which targets AVX2 + FMA3 and depends on the accuracy of VRCPPS/VRSQRTPS. Should I expect the implementation of these instructions on Haswell to be the same as on Ivy Bridge? Regards, Marat
Angelos P.Tue, April 30th 2013 - 6:33
Adding consecutive large numbers5
I am trying to write a simple assembly code in asm using the AVX instructions. I have seen a problem rising up while adding large numbers. The code is here: __asm__ __volatile__( "vzeroall\n\t" "movl $0, %%r9d\n\t" "movl $4, %%r10d\n\t" "leal (%%eax, %%r9d, 1), %%edx\n\t" "vbroadcastss (%%edx), %% ...

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