All Articles Tagged data
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| Replace a Set of Pointers With a Base Pointer to Reduce Data Bloat [Knowledgebase] Challenge Reduce data bloat due to the use of many pointers. Pointers in the Itanium® architecture are twice the size of pointers in 32-bit Intel® architecture, which may effectively double the... Posted: 2008-12-04 21:00:00 by kslewisx | data, Develop for Core processor, How-To |
| Manipulate Data Structure to Optimize Memory Use on 32-Bit Intel® Architecture [Knowledgebase] Challenge Improve memory utilization by manipulating data-structure layout. For certain algorithms, like 3D transformations and lighting, there are two basic ways of arranging the vertex data. The... Posted: 2008-12-02 00:00:00 by kslewisx | data, Develop for Core processor, How-To |
| Manipulate Data Structure to Optimize Memory Use on 32-Bit Architecture [Knowledgebase] Challenge Improve memory utilization by manipulating data-structure layout. For certain algorithms, like 3D transformations and lighting, there are two basic ways of arranging the vertex data. The... Posted: 2010-09-21 18:29:12 by kslewisx | data, Develop for Core processor, How-To |
| Manage Structure Padding to Avoid Data Bloat [Knowledgebase] Challenge Reduce or eliminate data bloat due to structure padding. With the Itanium® architecture, data boundaries are naturally aligned, instead of freely (any-byte) aligned as on 32-bit Intel®... Posted: 2009-03-08 21:00:00 by Jehny Nogueron (Intel) | data, Develop for Core processor, How-To |
| Loop Blocking to Optimize Memory Use on 32-Bit Architecture [Knowledgebase] Challenge Improve memory utilization by means of loop blocking. The main purpose of loop blocking is to eliminate as many cache misses as possible. Consider the following loop, as it exists before... Posted: 2009-03-06 00:00:00 by kslewisx | data, Develop for Core processor, How-To |
| Correct Endian Issues with Hex Constants Used as Byte Arrays [Knowledgebase] Challenge Modify code that includes hex constants used as byte arrays written for big-endian systems to run properly on Intel® architecture. Endianness refers to how a data element and its individual... Posted: 2008-11-20 21:00:00 by kslewisx | data, Develop for Core processor, How-To |
| Avoid Partial Memory Accesses on 32-Bit Intel® Architecture [Knowledgebase] Challenge Avoid partial memory accesses. Consider a case with large load after a series of small stores to the same area of memory (beginning at memory address mem). The large load will stall in this... Posted: 2009-03-02 00:00:00 by kslewisx | data, Develop for Core processor, How-To |
| Intel Software Network at SIGGRAPH 2008[Knowledgebase] Get Your Visual Adrenaline Flowing! See what we're up to at SIGGRAPH in our overview PDF (383kb). Also, view our paper released August 4, 2008: "Larrabee: A Many Core x86... Posted: 2009-06-19 00:00:00 by Gina Bovara (Intel) | conferences, data, larrabee, siggraph, vcsource_domain_graphics, vcsource_domain_media, vcsource_index, vcsource_type_news, visual computing |