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| Link/Url | Tags |
|---|---|
| 英特尔软件网路在SIGGRAPH 2008活动概览 [Knowledgebase] 体验令你心跳加速的视觉计算技术! 了解我们在SIGGRAPH 的主要活动细节 PDF (383kb). 同时浏览我们于八月4日发布的论文: "Larrabee: 一个用 ... Posted: 2008-08-14 15:44:12 by | Events, data, siggraph, conferences, larrabee, visual computing |
| Avoid Partial Memory Accesses on 32-Bit Intel® Architecture [Knowledgebase] Challenge Avoid partial memory accesses. Consider a case with large load after a series of small stores to the same area of memory (beginning at memory address mem). The large load will stall in ... Posted: 2009-03-02 08:58:14 by | data, Develop for Core processor, How-To |
| Correct Endian Issues with Hex Constants Used as Byte Arrays [Knowledgebase] Challenge Modify code that includes hex constants used as byte arrays written for big-endian systems to run properly on Intel® architecture. Endianness refers to how a data element and its indiv ... Posted: 2008-11-21 14:08:12 by | data, Develop for Core processor, How-To |
| Loop Blocking to Optimize Memory Use on 32-Bit Architecture [Knowledgebase] Challenge Improve memory utilization by means of loop blocking. The main purpose of loop blocking is to eliminate as many cache misses as possible. Consider the following loop, as it exists befor ... Posted: 2009-03-06 08:26:12 by | data, Develop for Core processor, How-To |
| Manage Structure Padding to Avoid Data Bloat [Knowledgebase] Challenge Reduce or eliminate data bloat due to structure padding. With the Itanium® architecture, data boundaries are naturally aligned, instead of freely (any-byte) aligned as on 32-bit Inte ... Posted: 2009-03-09 09:37:38 by | data, Develop for Core processor, How-To |
| Manipulate Data Structure to Optimize Memory Use on 32-Bit Architecture [Knowledgebase] Challenge Improve memory utilization by manipulating data-structure layout. For certain algorithms, like 3D transformations and lighting, there are two basic ways of arranging the vertex data. Th ... Posted: 2009-03-09 10:38:24 by | data, Develop for Core processor, How-To |
| Manipulate Data Structure to Optimize Memory Use on 32-Bit Intel® Architecture [Knowledgebase] Challenge Improve memory utilization by manipulating data-structure layout. For certain algorithms, like 3D transformations and lighting, there are two basic ways of arranging the vertex data. Th ... Posted: 2008-12-02 09:12:14 by | data, Develop for Core processor, How-To |
| Replace a Set of Pointers With a Base Pointer to Reduce Data Bloat [Knowledgebase] Challenge Reduce data bloat due to the use of many pointers. Pointers in the Itanium® architecture are twice the size of pointers in 32-bit Intel® architecture, which may effectively double the ... Posted: 2008-12-05 13:11:27 by | data, Develop for Core processor, How-To |