The task of constructing of identifying sequences for synchronous sequential circuits is one of the central problems in the design process. Genetic algorithm (GA) is one of the possible solutions of this task. It uses simulation of digital circuits to value the quality of potential solutions. Due this fact GA of input sequences generation are very slowly. In this paper we propose parallel versions of GA of this type that adapted for multi-core workstations. In our approach we organize several parallel threads.
Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.
Performance analysis is an essential step in the development of HPC codes. It will even gain in importance with the rising complexity of machines and applications that we are seeing today. Many tools exist to help with this analysis, but the user is too often left alone with interpreting the results. In this tutorial we will provide a practical road map for the performance analysis of HPC codes and will provide users step by step advice on how to approach the optimization of their codes as well as on how to investigate observed performance bottlenecks in detail.
A new goal for my educational efforts coalesced today: fostering viral education.
I've known for awhile that I could sometimes infect a student; get them working on a problem/project/idea, where they spend lots of time outside of class on this effort. It hadn't occurred to me till today that this notion could be generalized to one student infecting another student.
The culprit catalyst has a two word title: Project Euler.