itanium
| Link/Url | Tags |
|---|---|
| Porting 32-bit Applications to the Itanium® Architecture [Knowledgebase] Introduction These labs provide best known methods for porting your application. Sample Code is included for you to try out the concepts. You will need access to an Itanium® 2-based system to practi ... Posted: 2009-08-21 14:35:35 by | itanium, xeon, Code |
| CPUID for x64 Platforms and Microsoft Visual Studio* .NET 2005 [Knowledgebase] When targeting x64 platforms in Visual Studio .NET* 2005, programmers are no longer able to use inline assembly code as they did for 32-bit code. This forces the programmer to either rely on C/C++ cod ... Posted: 2009-01-23 09:04:20 by Eric Palmer (Intel) | itanium, Code |
| Efficiency and Coding Practices: Maximum Efficiency for Itanium® Architecture [Knowledgebase] Overview All programs can benefit from specific tuning efforts aimed at extracting maximum performance on any given processor architecture. While it is relatively easy to derive peak performance valu ... Posted: 2008-05-05 13:42:49 by | itanium, Code |
| Short Data Segment Overflow Error on Linux* 64 on Itanium® Architecture [Knowledgebase] by Seung-Woo Kim Abstract It is possible to produce a short data segment overflow link error on Intel® Itanium® Architecture on Linux* 64 platforms when building very large static images. This pro ... Posted: 2009-08-25 12:35:43 by Seung-woo Kim (Intel) | itanium, Code, Linux |
| Performance Scaling in the Multi-Core Era [Knowledgebase] by Robert Shiveley Introduction New strategies are needed to maintain historic rates of performance and price/performance improvement. We take a closer look at the Intel® Itanium® processor. "In ... Posted: 2008-10-27 17:42:18 by Robert Shiveley (Intel) | itanium, Multi-threading |
| Access a 32-Bit DLL from a Native 64-Bit Process on Intel Architecture [Knowledgebase] Challenge Access an IA-32 DLL from a native Intel® Itanium® architecture Process. Porting an application to the Itanium architecture has many benefits, including the ability to take advantage o ... Posted: 2009-07-08 12:38:37 by | itanium, 64-bit Coding, How-To |
| Avoid Memory-Coding Errors on 64-Bit Intel® Architecture [Knowledgebase] Challenge Avoid performance and security issues associated with memory-coding errors. Memory-coding errors lead directly to security vulnerabilities. Memory-access miscodings appear to be respons ... Posted: 2008-11-19 16:44:01 by | itanium, 64-bit Coding, How-To |
| Ensure that the 64-Bit Compiler Can Find Type Mismatches [Knowledgebase] Challenge Avoid type-mismatch errors due to the use of #define to define constants with the 64-bit Intel® architecture. In the following code, where #define is used for a constant, the compiler ... Posted: 2008-11-24 15:24:34 by | itanium, 64-bit Coding, How-To |
| Handle Win64 Errors Related to Obsolete Win32 Constants [Knowledgebase] Challenge Address Win64* compilation errors related to old Win32* constants. A few of the constants used with the Win32 APIs have been modified for Win64; as a result, using the old constants wil ... Posted: 2008-11-25 10:58:38 by | itanium, 64-bit Coding, How-To |
| Handle Win64 printf or wsprintf Warnings [Knowledgebase] Challenge Address Win64* compilation warnings related to improper use of Win64 printf or wsprintf format specifiers. Using improper format specifiers in printf or wsprintf will generate warnings. ... Posted: 2008-11-25 12:37:56 by | itanium, 64-bit Coding, How-To |
| Handle Win64 Truncation Warnings [Knowledgebase] Challenge Address Win64* compilation warnings related to truncation. Most of the warnings that you encounter when compiling for Win64 are truncation-related warnings (conversion from INT64 to int ... Posted: 2008-11-25 12:56:44 by | itanium, 64-bit Coding, How-To |
| Manage Thread-Stack Size in 64-bit UNIX [Knowledgebase] Challenge Determine the default thread-stack size for a particular implementation of UNIX and adjust that size in your application. The operating system permits multiple threads of execution with ... Posted: 2009-03-09 09:43:15 by | itanium, 64-bit Coding, How-To |
| Manage Thread-Stack Size in Windows 2000 (64-bit) [Knowledgebase] Challenge Automatically allocate stack space in Windows 2000 (64-bit) applications to avoid stack overflow. The operating system permits multiple threads of execution within a process's address s ... Posted: 2009-03-09 09:51:45 by | itanium, 64-bit Coding, How-To |
| Select a Win64 Porting Model [Knowledgebase] Challenge Choose the appropriate model for porting an application from the Win32 environment to Win64. Win64 provides four different porting options. The correct option for a given application de ... Posted: 2009-03-10 15:58:57 by | itanium, 64-bit Coding, How-To |
| Support Hex Constants on 64-Bit Intel Architecture [Knowledgebase] Challenge Modify code to support the use of integer-constant-type suffixes on 64-bit Intel® architecture. If a piece of code uses hex constants to generate a particular value, you might need to ... Posted: 2009-03-11 09:33:22 by | itanium, 64-bit Coding, How-To |
| Use Appropriate Data Types to Manage 64-bit Data Size [Knowledgebase] Challenge Ensure that you are using 32-bit or 64-bit data types as appropriate for your variables. Caution in this area conserves resources and avoids data bloat. Solution If a variable wil ... Posted: 2009-03-11 16:50:54 by | itanium, 64-bit Coding, How-To |
| Use Make files to Resolve Win64 Porting Issues [Knowledgebase] Challenge Identify issues associated with porting an application to the Win64 environment. Once an appropriate model has been chosen for porting an application to the Win64 environment, which is ... Posted: 2009-03-11 17:41:08 by | itanium, 64-bit Coding, How-To |
| Guide Compilers to Optimize Inner Loops for 64-Bit Intel Architecture [Knowledgebase] Challenge Guide the compiler to perform the proper amount of optimization on an inner loop. One of the quickest ways to find an inner loop in an assembly language listing is to look for sections ... Posted: 2009-03-03 15:55:07 by | itanium, How-To, compiler |
| Improve Performance on 64-Bit Intel Architecture with Intel C++ Compiler for Linux Options [Knowledgebase] Challenge Use the options built into the Intel® C++ Compiler for Linux to improve performance on the Itanium® processor. The Intel compilers have robust feature sets to support optimization at ... Posted: 2009-01-26 15:46:32 by | itanium, How-To, compiler |
| Resolve Cache Misses on 64-Bit Intel Architecture [Knowledgebase] Challenge Resolve cache misses that cause a significant number of stall cycles. These occur when data is not in the desired cache and data retrieval requires access to a slower cache, memory, or ... Posted: 2009-03-10 13:39:24 by | itanium, How-To, compiler |
| Use Intel Compilers Successfully for 64-Bit Intel Architecture [Knowledgebase] Challenge Use the Intel® Compilers for maximum performance. This item answers common questions about using the Intel compilers, and it also gives troubleshooting and optimization techniques. ... Posted: 2009-03-11 17:11:32 by | itanium, How-To, compiler |
| Use Pragmas with the Intel® C++ Compiler for Linux on 64-Bit Architecture [Knowledgebase] Challenge Use pragmas with the Intel® C++ Compiler for Linux to improve performance on the Itanium® processor. A pragma is a statement used to suggest that a compiler optimization be performed ... Posted: 2009-01-26 16:06:11 by | itanium, How-To, compiler |
| Allocate Memory Optimally to the Bufferpool and Sortheap for DB2 Databases on Itanium-Based Systems [Knowledgebase] Challenge Allocate memory to the bufferpool and sortheap for high performance of IBM DB2* databases on Itanium®-based systems. DB2 allocates memory mainly on the logical-node level for bufferpoo ... Posted: 2009-03-01 22:02:48 by | itanium, DB2, How-To |
| Configure Striping Size and Eventsize for IBM DB2 Databases on Itanium-Based Systems [Knowledgebase] Challenge Configure striping size and eventsize for IBM DB2* Databases to produce high performance on Itanium®-based systems. The organization of data on the disks is an important factor for ben ... Posted: 2009-03-02 12:50:57 by | itanium, DB2, How-To |
| Optimally Define IBM DB2 Bufferpool Page Size for Itanium-Based Systems [Knowledgebase] Challenge Define bufferpool size for IBM DB2 databases to produce high performance on Itanium®-based systems. Controlling the size of the bufferpool pages is a key performance-tuning measure. A ... Posted: 2009-03-09 14:22:42 by | itanium, DB2, How-To |
| Develop Coding Best Practices Targeting Compilers for 64-Bit Intel® Architecture [Knowledgebase] Challenge Write code that makes the best use of the compiler's capabilities for 64-bit Intel® architecture. In addition to implementation-specific optimizations, coding practices that target com ... Posted: 2009-03-02 14:53:59 by | itanium, Itanium Coding, How-To |
| Implement Efficient MADD Operations on 64-Bit Intel Architecture [Knowledgebase] Challenge Implement a multiply and add operation efficiently on 64-bit Intel® architecture. Integer matrix multiplication is a common procedure that is used generically to explore options for op ... Posted: 2009-03-04 08:45:56 by | itanium, Itanium Coding, How-To |
| Include Optimized Assembly Code in Compilation for 64-Bit Intel® Architecture [Knowledgebase] Challenge Include assembly code in compilation and determine its effectiveness. Once you have optimized assembly code by hand, you must include that optimized assembly in the compilation and then ... Posted: 2009-03-05 09:25:07 by | itanium, Itanium Coding, How-To |
| Locate Code in Assembly Language for 64-Bit Intel® Architecture [Knowledgebase] Challenge Locate code in an assembly language listing that corresponds to a specific passage of source code. The importance of interpreting compiler-produced assembly language code is the fact th ... Posted: 2009-03-06 08:17:03 by | itanium, Itanium Coding, How-To |
| Manage Jump Buffer Size for Itanium Architecture [Knowledgebase] Challenge Manually allocate a jump buffer to ensure that it has adequate space to accommodate sufficient pointers for Itanium® architecture. When using a non-ANSI-defined jmp_buf data type, code ... Posted: 2009-03-06 09:00:49 by | itanium, Itanium Coding, How-To |
| Support Integer-Constant-Type Suffixes on 64-Bit Architecture [Knowledgebase] Challenge Modify code to support the use of integer-constant-type suffixes on 64-bit Intel® architecture. If integer-constant-type suffixes are used in the code, you might need to modify the cod ... Posted: 2009-03-11 09:40:13 by | itanium, Itanium Coding, How-To |
| Trace the Logic in an Assembly Code Listing for 64-Bit Intel Architecture [Knowledgebase] Challenge Analyze compiler-generated assembly language to determine the logic of critical sections of code. A structured methodology for gaining an understanding of the assembly code is essential ... Posted: 2009-03-11 11:52:10 by | itanium, Itanium Coding, How-To |
| Use Code from the Intel® Itanium Processor on the Itanium 2 Processor [Knowledgebase] Challenge Get better performance when moving an application written for the Intel® Itanium® processor to the Itanium® 2 processor. The second-generation Itanium processor, the Itanium 2 proces ... Posted: 2009-03-11 16:55:17 by | itanium, Itanium Coding, How-To |
| Use Code Guards to Compile 32-bit Code for the Itanium Architecture [Knowledgebase] Challenge Designate specific blocks of 32-bit code to be compiled for the Itanium® architecture. Source code often needs local customization based on the target platform. Solution Use code ... Posted: 2009-03-11 16:59:49 by | itanium, Itanium Coding, How-To |
| Use Intel Performance Libraries on 64-Bit Architecture [Knowledgebase] Challenge Implement code form Intel® Performance Libraries to optimize code associated with hotspots for the 64-bit Intel® architecture. Intel has developed highly optimized standardized routin ... Posted: 2009-03-11 17:28:30 by | itanium, libraries, How-To |
| Ensure Accurate Data Access When Using An Offset with Itanium Architecture [Knowledgebase] Challenge Avoid misidentifying data fields due to hard-coded offsets being used to access data structures with Itanium® architecture. The following code contains a hard-coded offset to access ... Posted: 2009-03-02 15:50:56 by | itanium, Memory Access, How-To |
| Identify Bank/Address Conflicts on 64-Bit Intel Architecture [Knowledgebase] Challenge Identify and locate conflicts in the EXE pipeline. Microprocessor cache architectures frequently have access structures that allow for very low latencies, but in some circumstances, thi ... Posted: 2009-03-03 16:42:43 by | itanium, Memory Access, How-To |
| Quantify Integer Bank-Conflict Penalties on 64-Bit Intel Architecture [Knowledgebase] Challenge Measure the performance penalty associated with L2 bank conflicts on integer-data loads. Access to cacheable integer data always goes through the L1D cache. This complicates the issue o ... Posted: 2009-03-10 11:12:21 by | itanium, Memory Access, How-To |
| Remove Many Bank Conflicts on 64-Bit Intel® Architecture [Knowledgebase] Challenge Remove bank conflicts from high-level loops. Removing bank conflicts is, in many cases, rather simple. Consider the following double-precision matrix multiply in Fortran: Do k= ... Posted: 2009-03-10 11:53:42 by | itanium, Memory Access, How-To |
| Resolve Address Conflicts on 64-Bit Architecture [Knowledgebase] Challenge Resolve address conflicts that cause a significant number of stall cycles. Cache misses occur when data is not in the desired cache and data retrieval requires access to a slower cache, ... Posted: 2009-03-10 13:33:41 by | itanium, Memory Access, How-To |
| Resolve Data-Alignment Errors for the Itanium Architecture [Knowledgebase] Challenge Avoid program exceptions associated with misaligned data objects in the 64-bit Intel® architecture. Under both Linux* and Win64*, developers will often encounter data-alignment errors ... Posted: 2009-03-10 13:43:53 by | itanium, Memory Access, How-To |
| Short Data Segment Overflow Errors on 64-Bit Architecture [Knowledgebase] Challenge Solve a potential short data segment overflow link error on Intel® Itanium® Architecture on Linux* 64 platforms when building very large static images. This problem exists on Windows* ... Posted: 2009-01-27 16:09:44 by | itanium, Memory Access, How-To |
| Analyze Memory Accesses on 64-Bit Intel Architecture [Knowledgebase] Challenge Determine what memory accesses are causing EXE pipeline stalls accumulated by the BE_EXE_Bubble counter. Most memory-access stall cycles are accumulated by the BE_EXE_Bubble counter. Th ... Posted: 2009-03-01 22:13:26 by | itanium, performance, How-To |
| Code Timing and Profiling for Linux on 64-Bit Intel® Architecture [Knowledgebase] Challenge Measure the time a program and its functions take to execute as part of the diagnosis phase of performance optimization. Such measurements are extremely valuable as a simple means to be ... Posted: 2009-03-02 12:44:28 by | itanium, performance, How-To |
| Develop an Execution-Time Benchmark on 64-Bit Intel Architecture [Knowledgebase] Challenge Develop a benchmark to measure the execution time of the piece of code you are optimizing. This is essential to determine whether your code changes are helping or hurting performance. M ... Posted: 2009-03-02 14:48:42 by | itanium, performance, How-To |
| Handle Streaming Data Optimally on 64-Bit Architecture [Knowledgebase] Challenge Handle long, high-bandwidth data streams optimally with the Intel® Itanium® processor. Proper utilization of the lfetch instructions is vital to optimal handling of streaming data. ... Posted: 2009-03-03 15:58:05 by | itanium, performance, How-To |
| Identify Back-End Bubbles on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify a processor back-end bubble on the Intel® Itanium® processor. A 'bubble' is defined as any delay in the processor. The 'back end' is the place where instructions are retired ... Posted: 2008-11-25 16:16:39 by | itanium, performance, How-To |
| Improve Code Based on Root-Cause Analysis on 64-Bit Intel® Architecture [Knowledgebase] Challenge Improve the efficiency of code based on root-cause analysis of back-end bubbles. That analysis is covered in a separate item How to Perform Back-End Bubble Root-Cause Analysis on 64-Bit ... Posted: 2008-11-25 16:26:53 by | itanium, performance, How-To |
| Improve Performance on 64-Bit Architecture of Applications with Many Small Functions [Knowledgebase] Challenge Improve application performance in programs that contain many frequently used small to medium-sized functions. This characteristic is very common in object-oriented C++ programs that im ... Posted: 2009-03-05 09:14:06 by | itanium, performance, How-To |
| Increase the Frequency of First-Level Instruction-Cache Hits on 64-Bit Intel Architecture [Knowledgebase] Challenge Increase the frequency with which the first-level instruction cache (L1D) is a hit for integer data. This optimization is key to achieving good performance on the Intel® Itanium® proc ... Posted: 2009-03-05 09:29:50 by | itanium, performance, How-To |
| Instruction Latencies in Assembly Code for 64-Bit Intel® Architecture [Knowledgebase] Challenge Optimize assembly-language code for the Itanium® processor family in terms of instruction latencies. The latency of an instruction is the length of time that has elapsed from when the ... Posted: 2009-03-05 09:39:07 by | itanium, performance, How-To |
| Perform Back-End Bubble Root-Cause Analysis on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify the root cause of a back-end processor bubble on the Intel® Itanium® processor. A separate item, How to Identify Back-End Bubbles on 64-Bit Intel® Architecture, shows how to ... Posted: 2009-01-16 10:55:45 by | itanium, performance, How-To |
| Perform Code Timing and Profiling for Linux on 64-Bit Architecture [Knowledgebase] Challenge Measure the time a program and its functions take to execute as part of the diagnosis phase of performance optimization. Such measurements are extremely valuable as a simple means to be ... Posted: 2009-01-26 15:58:59 by | itanium, performance, How-To |
| Prepare Applications for Optimization on 64-Bit Intel® Architecture [Knowledgebase] Challenge Prepare applications for optimization on the Intel® Itanium® processor family. The first issue in getting high performance code on Itanium-based systems is to get the code ported or w ... Posted: 2009-03-09 17:30:01 by | itanium, performance, How-To |
| Prioritize Bottlenecks on the Itanium Processor [Knowledgebase] Challenge Prioritize Performance Bottlenecks in terms of their impact on performance to support their resolution in order of importance. The key to optimizing an application is to use performance ... Posted: 2009-03-09 17:40:57 by | itanium, performance, How-To |
| Quantify Floating-Point Bank-Conflict Penalties on 64-Bit Intel Architecture [Knowledgebase] Challenge Measure the performance penalty associated with bank conflicts on floating-point loads. If you are dealing with a looping algorithm and have unrolled the loops (or if the compiler has d ... Posted: 2009-03-10 11:03:29 by | itanium, performance, How-To |
| Quantify the Penalty of Branch Misprediction on 64-Bit Architecture [Knowledgebase] Challenge Determine the performance penalty associated with the misprediction of a conditional branch on a processor based on 64-bit Intel® architecture. A separate item, How to Identify Branch ... Posted: 2009-02-27 10:11:36 by | itanium, performance, How-To |
| Resolve Back-End Bubbles on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify back-end bubbles (processor delays) in 64-bit applications and resolve them. Like any hardware platform, the Intel® Itanium® processor is dependent for performance upon the q ... Posted: 2008-12-05 13:22:18 by | itanium, performance, How-To |
| Schedule Instructions Optimally on 64-Bit Intel® Architecture [Knowledgebase] Challenge Schedule instructions properly for optimal performance on the Intel® Itanium® processor. Optimal scheduling will minimize the chances of implicit stops or unexpected dispersal-related ... Posted: 2009-03-10 15:21:56 by | itanium, performance, How-To |
| Develop Linux Applications for Compatibility between Itanium-Based Systems and the IBM POWER architecture [Knowledgebase] Challenge Help to ensure that Linux applications under development are cross-compatible between Itanium®-based systems and the IBM POWER* architecture. Solution Write endian-neutral code, ... Posted: 2009-03-02 14:58:22 by | itanium, Porting, How-To |
| Port Linux Applications [Knowledgebase] by Stephen Satchell How to Port Linux* Applications Porting your Linux* applications to the Itanium® architecture can be straightforward if you follow these suggestions, which highlight the key ... Posted: 2009-03-09 17:15:07 by | itanium, Porting, How-To |
| Analyze Bottlenecks from 64-bit Pipeline Stalls at the DET Stage [Knowledgebase] Challenge Identify dominant sources of performance bottlenecks accumulated by the BE_L1D_FPU_Bubble event, which accumulates stall cycles caused by the micropipelines associated with the L1D and ... Posted: 2008-11-19 15:08:13 by | itanium, Stall Analysis, How-To |
| Analyze Pipeline Flush Losses on 64-Bit Intel Architecture [Knowledgebase] Challenge Determine the causes of cycles lost due to pipeline flushes, based on events accumulated by the BE_Flush_Bubble counter. These stalled cycles are comprised of the following: Branch ... Posted: 2009-03-01 22:19:02 by | itanium, Stall Analysis, How-To |
| Analyze Pipeline Stalls on 64-Bit Intel Architecture [Knowledgebase] Challenge Identify and categorize the causes of pipeline stalls for maximum performance on the Itanium® processor and Itanium® processor. The objective of microarchitectural optimization is to ... Posted: 2009-03-01 22:24:45 by | itanium, Stall Analysis, How-To |
| Characterize Application Performance with Stall Events on 64-Bit Architecture [Knowledgebase] Challenge Use front-end stall-cycle events and back-end stall-cycle events to characterize the performance of an application on the Intel® Itanium® Processor. The Itanium® 2 Processor separate ... Posted: 2009-03-02 12:35:55 by | itanium, Stall Analysis, How-To |
| Functional Unit Stalls on 64-Bit Intel® Architecture [Knowledgebase] Challenge Minimize inefficiencies due to functional-unit latency stalls. Computers require functional-unit latency stalls to ensure that results are computed correctly. In a chain of instructions ... Posted: 2009-03-03 15:29:29 by | itanium, Stall Analysis, How-To |
| Quantify Memory-Stall Penalties on 64-Bit Architecture [Knowledgebase] Challenge Determine memory-access stall penalties due to simple cache misses. Whenever a load instruction attempts to access data from a data cache array that does not contain the desired data, i ... Posted: 2009-03-10 11:18:53 by | itanium, Stall Analysis, How-To |
| Register-Stack Engine Stalls on 64-Bit Architecture [Knowledgebase] Challenge Identify the source of stall cycles due to invocation of the Register Stack Engine (RSE). There are 96 general registers used for the register stacks. A deep call stack or a call stack ... Posted: 2009-03-10 11:48:52 by | itanium, Stall Analysis, How-To |
| Resolve Memory Access Stalls on 64-Bit Intel® Architecture [Knowledgebase] Challenge Resolve memory access stalls in the EXE pipeline stage on 64-Bit Intel® Architecture. Memory access stalls occur when the data is not available in the caches as expected. The instructi ... Posted: 2009-03-10 13:56:17 by | itanium, Stall Analysis, How-To |
| Itanium Awareness? [Forums] I'm wondering what people think about teaching how to program Itanium-based systems to colleges (especially the folk from Intel) The reason I'm saying this is because x86 is reaching its end limits f ... Posted: 2008-10-23 22:50:59 by Adam Kachwalla | itanium, education |