All Articles Tagged Architecture
| Link/Url | Tags |
|---|---|
| Intel Architecture and Processor Identification With CPUID Model and Family Numbers[Knowledgebase] This article is intended to aid software developers in understanding the "big picture" of Intel®'s recent architecture and processor releases. The "tick tock" model adds predictability to Intel®'s architecture... Posted: 2011-10-04 00:00:00 by Hussam Mousa (Intel) | Architecture, Architecture codename identification, CPUID, cpuid family code, cpuid model number, cpuid processor signature, CPUID String, microarchitecture, Processor codename identification, Processor identification |
| Benefits of Parallel Studio XE on Intel MIC Architecture[Videos] This video features a highly parallelized programming demo running on Intel Many Integrated Core (MIC) Architecture from SC10. Posted: 2010-12-27 08:36:24 | Architecture, demo, intel software tools, Many Integrated Core, manycore, MIC, multicore, Parallel Studio XE, SC10, Software Tools, tools |
| Suddenly All Computing is Parallel: Seizing Opportunity Amid the Clamor Part 4[Videos] Michael Wrinn's keynote from SIGCSE 2010. The shift in computing hardware to parallel systems is well underway. Sequential chips are no longer designed, and the proud era of von Neumann architecture passes... Posted: 2010-04-01 12:08:15 | Academic, Architecture, education, Innovative Software Education, Intel Software Network, Michael Wrinn, Parallel Programming, tools, Training |
| Suddenly All Computing is Parallel: Seizing Opportunity Amid the Clamor Part 1[Videos] The shift in computing hardware to parallel systems is well underway. Sequential chips are no longer designed, and the proud era of von Neumann architecture passes into history. Foundational change of... Posted: 2010-04-01 11:39:16 | Architecture, Innovative Software Education, keynote, Michael Wrinn, Parallel Programming, Parallel Programming & Multi-Core, SIGCSE, SIGCSE 2010, tools |
| Performance and Portability Benefits of Ct[Knowledgebase] PerformanceIntel Ct is scalable to large problems. The runtime manages data to directly address memory bottlenecks. Furthermore, the Intel Ct runtime compilation process eliminates modularity overhead.... Posted: 2010-03-02 00:00:00 by Noah Clemons (Intel) | Architecture, BLAS, compilation, compiler, FFT, fusion, IPP, lapack, memory bottlenecks, MKL, modularity, runtime, scalability, simd-ization, TBB, Vectorization |
| Intel Architectural Resources for Academia[Knowledgebase] During the recent SIGCSE 2008 in Chattanooga, I received queries from a number of professors about the best place to find technical (no marketing) articles describing processor architecture at the register... Posted: 2009-05-28 00:00:00 by Paul Steinberg (Intel) | Architecture, Core, processor, software, UEFI |
| Netburst and Core[Forums] First i am sorry if i am in the wrong dorum section.But i need to do a architecture comparison between Netburst and Core architectures.But i dont know and cant find any relevant data for that matter.So... Posted: 2009-04-27 04:25:08 | Architecture, Compare, Core, netburst |
| buffer overflow and caches[Forums] i have a small doubt concerning the behavior of cache in a buffer overflow attack.consider the following sequence of events:1. suppose stack is in d-cache.2. assume no context switch occurs.3. return statement... Posted: 2009-04-09 11:49:14 | Architecture |
| Bootcamp: Intel® Active Management Technology (Intel® AMT) OvervArchitecture Overview[Videos] The Intel® Active Management Technology (Intel® AMT) Architecture presentation provides an overview of all the key features of Intel AMT including the features introduced in Intel AMT 2.0/3.0. The presentation... Posted: 2008-12-12 17:34:35 | Architecture, Intel AMT |