All Articles Tagged performance
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| movaps running very slow[Forums] I was doing some simple timing tests and I noticed that movaps, and most of the sse floating point instructions, were running slow.I have my code below. I tested doing a bunch of NOPs, another test with... Posted: 2012-03-12 22:24:32 | movaps, performance, SSE |
| Performance of Compiler Location on Cluster[Forums] Hello,Can anyone tell me what type of effect the location of compiliers on a cluster has on Software compiled with the compiler has? Im thinking about two cases. First, a complier is shared across all... Posted: 2012-02-09 22:18:19 | Cluster, compiler, location, NFS, performance |
| Technical Presentation: Future-Proof Your Application\'s Performance With Vectorization[Forums] First Session Registration is closed : Wednesday, February 15, 2012, 9:00AM - 10:00AM PST (GMT-8)Register for Repeat Session : Wednesday, February 22, 2012, 9:00AM - 10:00AM PST (GMT-8)You've heard... Posted: 2012-02-08 12:02:30 | performance, Vectorization, webinar |
| disruptor pattern vs tbb queus/pipelines[Forums] Hi, Disruptor performance tests shows some signification advantages over locked queues. Has anyone done any comparision between disruptor pattern's ring buffer approach vs tbb concorrent queues to... Posted: 2011-12-04 20:56:30 | disruptor, performance, pipeline, TBB |
| Using Intel(R) VTune(TM) Amplifier XE to Tune Software on the 2nd Generation Intel(R) Core(TM) Processor Family[Knowledgebase] Download this guide (see Article Attachments, below) to learn how to identify performance issues on software running on the 2nd generation Intel® Core™ processor family (based on Intel® Microarchitecture... Posted: 2011-06-15 00:00:00 by Shannon Cepeda (Intel) | optimization, performance, Sandy Bridge, software, Tuning, Vtune |
| Slow performance compared to raw pthreads[Forums] I am seeing some severe performance problems when compared to using raw pthreads. TBB is about 10% of the speed of pthreads. vmstat 1 shows that there are a lot of interrupts for TBB and hardly any... Posted: 2011-03-15 17:10:50 | linux, performance |
| dummy arguments and memory footprint[Forums] Can someone please remind me if Fortran procedure arguments are passed by reference or by value, I think I have been confusing c and fortran in this regard. Also, does this change at all with attributes... Posted: 2011-01-31 14:33:03 | dummy argument, memory usage, performance |
| Intel® Integrated Performance Primitives (Intel® IPP) - Boosting Application Performance [PDF][Knowledgebase] White Paper - Boosting Application Performance Using Intel® Performance Libraries Boosting Application Performance Using Intel® Performance Libraries File Name: 219359_wp_boosting_app_perf_web.pdf... Posted: 2008-09-16 09:00:00 by ISN Admin | IPP, performance |
| The Serial On-Ramp to the Multicore Highway: Preparing to Parallelize Code[Knowledgebase] Download Article Download The Serial On-Ramp to the Multicore Highway: Preparing to Parallelize Code [PDF 143KB]Without proper preparation, parallelizing code might provide no lift, or worse, it could... Posted: 2010-09-13 00:00:00 by Andrew Binstock | game development, hot spot, parallelization, performance, performance optimization, vcsource_domain_gamedev, vcsource_domain_graphics, vcsource_index, vcsource_os_windows, vcsource_platform_desktoplaptop, vcsource_product_vtunexe, vcsource_type_techarticle, visual computing, Vtune |
| Reliability, Availability, and Serviceability on Intel® Xeon® Processors[Videos] The latest Intel® Xeon® processors include an unprecedented number of transistors, and in addition to the dramatic increases in performance, they add RAS (Reliability, Availability and Serviceability)... Posted: 2010-09-08 13:24:19 | Intel Xeon processor, Machine Check Architecture, performance, RAS features, reliability |
| Productivity benefits of Intel Ct Technology[Knowledgebase] The key features and benefits of Intel Ct lie within the 3Ps. The first one is Productivity.Productivity– Intel Ct Integrates with existing IDEs, tools, and compilers In addition to working seamlessly... Posted: 2010-03-02 00:00:00 by Noah Clemons (Intel) | Ct, IPP, MKL, performance, portability, productivity, syntax, TBB |
| Threading Fortran applications for parallel performance on multi-core systems[Knowledgebase] Threading Fortran applications for parallel performance on multi-core systemsMost processors now come with multiple cores, and future increases in performance are expected to come mostly from increases... Posted: 2009-12-06 21:00:00 by Martyn Corden (Intel) | mult-core, parallel, performance, threading |
| 945GME texturing performance[Forums] Hi!I develop an embedded application based on the following prototype HW and SW components:* Intel Atom CPU* VGA compatible controller: Intel Corporation Mobile 945GME Express Integrated Graphics Controller... Posted: 2009-12-01 03:56:06 | cpu, GPU, performance, texturing |
| IBM DB2 9.7 on Intel Xeon Processor 5500 Series[Knowledgebase] Are you spending too much on your database? PROGRAMMING: Automated tuning features in DB2 9.7 outperformed expert IBM engineers. PERFORMANCE: Intel Xeon processor 5500 series delivers 9x the performance... Posted: 2009-09-18 00:00:00 by Cecilia Villalon (Intel) | database, performance, xeon |
| SSE optimizations and IEEE 754[Forums] Hi,I'm using the options below as my best tradeoff between SSE performance and IEEE 754 conformance. Are there any other flags I could add that would bring me even closer to precise arithmetic without... Posted: 2009-08-24 14:54:06 | IEEE floating point, performance, SSE |
| Power, Performance and Open Source[Videos] Ram Peddibhotla, Director of Intel’s Open Source Technology Center, discusses Intel’s longstanding contribution to the Open Source community in all areas of the stack to take best advantage of the... Posted: 2009-07-07 14:02:35 | open source, performance, Power |
| Optimizing Open Source Citrix Xen* Code Base for Intelligent Performance[Videos] As the number one contributor to the Open Source Citrix Xen* code base, Intel collaborated with Citrix to optimize their software to take full advantage of the intelligent performance, virtualization,... Posted: 2009-07-01 15:18:16 | Citrix, opensource, performance, Xen, xeon |
| New in Intel® MKL 10.2[Knowledgebase] New in Intel® MKL 10.2 Update 7: LAPACK: Threaded QR factorization with pivoting (DGEQP3) on Itanium® architecture PARDISO/DSS: Added true F90 overloaded API (see the Intel MKL reference manual... Posted: 2010-02-20 21:00:00 by Todd Rosenquist (Intel) | new features, performance |
| Performance problem involving mixed gcc/icc compilation[Forums] Greetings,I have been trying to use ICC on a large application and have comeacross some strange performance problems. I am using ICC 11.081,gcc 4.1.2p2 and Linux Red Hat Enterprise 5.I am compiling some... Posted: 2009-06-14 14:38:53 | gcc, gcc vs icc, performance |
| Infiniband-Intel MPI Performance MM5[Forums] Dear colleagues,we are working in an Infiniband DDR cluster with MM5. We are using the latest Intel MPI and Fortran, and our mm5.mpp has been compiled with the configuration suggested in this website.This... Posted: 2009-05-26 00:58:06 | InfiniBand, intel, MM5, performance |
| Putting -lm Before User Objects/Libraries on Link Line Can Impact Performance[Knowledgebase] Reference Number : DPD200121218Version : 11.0Operating System : Linux*Problem Description : Starting with 11.0.081, a fix was made to the compiler driver to link the Intel Math Library libimf... Posted: 2009-10-14 00:00:00 by Brandon Hewitt (Intel) | -lm, GNU, libimf, libm, library, math, performance, static |
| Opencv and IPP Face Detection comparison[Forums] I am using Opencv face detection but its both speed and performance are not satisfactor and now I am planning to use Intel IPP Face detection. Would you please tell me the major difference between Opencv... Posted: 2009-04-12 21:31:22 | cascade, Compare, detection, difference, Face, IPP, opencv, performance, Training, utility |
| 5 minutes to understand video series - Intel(R) Thread Checker[Videos] The "5 minutes to understand" series show how to use Intel(R) VTune(TM) Performance Analyzer, Thread Profiler and Thread Checker products. In these videos, you will learn the basics of the products and... Posted: 2008-12-11 03:22:51 | Intel Thread Checker, performance, Thread Profiler, tools, Visual Studio, Vtune |
| 5 minutes to understand video series - Intel(R) VTune Performance Analyzer[Videos] The "5 minutes to understand" series show how to use Intel(R) VTune(TM) Performance Analyzer, Thread Profiler and Thread Checker products. In these videos, you will learn the basics of the products and... Posted: 2008-12-11 02:59:45 | Intel VTune, performance, software, Vtune |
| Apple iPhone Performance Study[Knowledgebase] iPhone Performance Study Jailbreaking the iPhone To enable access to the phone’s OS, you need to “Jailbreak” it. The iPhone is essentially a mini-mac like OS so many things learned developing... Posted: 2008-10-10 00:00:00 by Dale Taylor (Intel) | apple, iphone, jailbreak, performance |
| IPhone Performance[Knowledgebase] To obtain some useful workload information required installing a termal application on my iPhone and then remoting to it so that I could run TOP and at least see the basic system statistics in real time... Posted: 2008-10-09 00:00:00 by Dale Taylor (Intel) | apple, iphone, performance, workload |
| Schedule Instructions Optimally on 64-Bit Intel® Architecture [Knowledgebase] Challenge Schedule instructions properly for optimal performance on the Intel® Itanium® processor. Optimal scheduling will minimize the chances of implicit stops or unexpected dispersal-related... Posted: 2009-03-10 01:00:00 by kslewisx | How-To, itanium, performance |
| Resolve Back-End Bubbles on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify back-end bubbles (processor delays) in 64-bit applications and resolve them. Like any hardware platform, the Intel® Itanium® processor is dependent for performance upon the quality... Posted: 2008-12-05 00:00:00 by kslewisx | How-To, itanium, performance |
| Quantify the Penalty of Branch Misprediction on 64-Bit Architecture[Knowledgebase] Challenge Determine the performance penalty associated with the misprediction of a conditional branch on a processor based on 64-bit Intel® architecture. A separate item, How to Identify Branch... Posted: 2009-07-31 21:00:00 by kslewisx | How-To, itanium, performance |
| Quantify Floating-Point Bank-Conflict Penalties on 64-Bit Intel Architecture [Knowledgebase] Challenge Measure the performance penalty associated with bank conflicts on floating-point loads. If you are dealing with a looping algorithm and have unrolled the loops (or if the compiler has done... Posted: 2009-03-10 01:00:00 by kslewisx | How-To, itanium, performance |
| Prioritize Bottlenecks on the Itanium Processor [Knowledgebase] Challenge Prioritize Performance Bottlenecks in terms of their impact on performance to support their resolution in order of importance. The key to optimizing an application is to use performance... Posted: 2009-03-09 01:00:00 by kslewisx | How-To, itanium, performance |
| Prepare Applications for Optimization on 64-Bit Intel® Architecture[Knowledgebase] Challenge Prepare applications for optimization on the Intel® Itanium® processor family. The first issue in getting high performance code on Itanium-based systems is to get the code ported or written... Posted: 2009-03-08 00:00:00 by kslewisx | How-To, itanium, performance |
| Perform Code Timing and Profiling for Linux on 64-Bit Architecture [Knowledgebase] Challenge Measure the time a program and its functions take to execute as part of the diagnosis phase of performance optimization. Such measurements are extremely valuable as a simple means to become... Posted: 2009-01-26 00:00:00 by kslewisx | How-To, itanium, performance |
| Perform Back-End Bubble Root-Cause Analysis on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify the root cause of a back-end processor bubble on the Intel® Itanium® processor. A separate item, How to Identify Back-End Bubbles on 64-Bit Intel® Architecture, shows how to... Posted: 2009-01-16 00:00:00 by kslewisx | How-To, itanium, performance |
| Instruction Latencies in Assembly Code for 64-Bit Intel® Architecture [Knowledgebase] Challenge Optimize assembly-language code for the Itanium® processor family in terms of instruction latencies. The latency of an instruction is the length of time that has elapsed from when the instruction... Posted: 2009-03-04 21:00:00 by kslewisx | How-To, itanium, performance |
| Increase the Frequency of First-Level Instruction-Cache Hits on 64-Bit Intel Architecture [Knowledgebase] Challenge Increase the frequency with which the first-level instruction cache (L1D) is a hit for integer data. This optimization is key to achieving good performance on the Intel® Itanium® processor... Posted: 2009-03-05 00:00:00 by kslewisx | How-To, itanium, performance |
| Improve Performance on 64-Bit Architecture of Applications with Many Small Functions[Knowledgebase] Challenge Improve application performance in programs that contain many frequently used small to medium-sized functions. This characteristic is very common in object-oriented C++ programs that implement... Posted: 2009-03-04 21:00:00 by kslewisx | How-To, itanium, performance |
| Improve Code Based on Root-Cause Analysis on 64-Bit Intel® Architecture [Knowledgebase] Challenge Improve the efficiency of code based on root-cause analysis of back-end bubbles. That analysis is covered in a separate item How to Perform Back-End Bubble Root-Cause Analysis on 64-Bit... Posted: 2008-11-25 00:00:00 by kslewisx | How-To, itanium, performance |
| Identify Back-End Bubbles on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify a processor back-end bubble on the Intel® Itanium® processor. A 'bubble' is defined as any delay in the processor. The 'back end' is the place where instructions are retired when... Posted: 2008-11-25 00:00:00 by kslewisx | How-To, itanium, performance |
| Handle Streaming Data Optimally on 64-Bit Architecture [Knowledgebase] Challenge Handle long, high-bandwidth data streams optimally with the Intel® Itanium® processor. Proper utilization of the lfetch instructions is vital to optimal handling of streaming data. Solution Make... Posted: 2009-03-03 00:00:00 by kslewisx | How-To, itanium, performance |
| Develop an Execution-Time Benchmark on 64-Bit Intel Architecture [Knowledgebase] Challenge Develop a benchmark to measure the execution time of the piece of code you are optimizing. This is essential to determine whether your code changes are helping or hurting performance. Most... Posted: 2009-03-02 00:00:00 by kslewisx | How-To, itanium, performance |
| Code Timing and Profiling for Linux on 64-Bit Intel® Architecture [Knowledgebase] Challenge Measure the time a program and its functions take to execute as part of the diagnosis phase of performance optimization. Such measurements are extremely valuable as a simple means to become... Posted: 2009-03-02 00:00:00 by kslewisx | How-To, itanium, performance |
| Analyze Memory Accesses on 64-Bit Intel Architecture [Knowledgebase] Challenge Determine what memory accesses are causing EXE pipeline stalls accumulated by the BE_EXE_Bubble counter. Most memory-access stall cycles are accumulated by the BE_EXE_Bubble counter. This... Posted: 2009-03-01 00:00:00 by kslewisx | How-To, itanium, performance |
| David Mackay, Guru Intel Performance Analysis & Threading Lab: Intel Top Five Take Five Videos[Videos] Meet David Mackay, PhD, Manager of Intel's Performance Analysis & Threading Lab Consulting Group. Posted: 2008-05-30 19:54:51 | intel, performance, software, threading |
| Writing Code to Reveal the Performance Details of Mobile Processors[Knowledgebase] Introduction Calculations reveal the relationships between power, clock speed, and frequencyby Richard WintertonJames Joule developed the formula for power dissipation (P = I²R), which states that power... Posted: 2008-10-02 21:00:00 by Richard Winterton (Intel) | Code, Mobility, performance, Power |
| Measure Code Sections Using The Enhanced Timer[Knowledgebase] Introduction Learn how to accurately measure events of short duration using the Enhanced Timer.To measure the performance of an application, it is common to time sections of code where hotspots or... Posted: 2009-01-13 14:35:55 by Khang Nguyen (Intel) | Code, performance |
| Welcome to the Intel C++ Compiler Forum![Forums] Hello,I welcome you to the Intel C++ compiler discussion forum.You will like this forum if you are a developer interested in C++, parallelism and performance optimization.Cheers!Ganesh Posted: 2008-09-26 15:02:32 | C++, compiler, optimization, performance |