All Articles Tagged cache
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| Cache Identifier[Forums] Hi everyone!I'd like to find out which cores share a particular cache. With the 'cpuid' command I found lots of useful information, but I still need some sort of unique cache identifier to... Posted: 2012-03-28 07:42:53 | cache, CPUID, hierarchy, identifier, sharing |
| How to discover which caches (L1,L2,L3) are shared by which HW threads (cores) ?[Forums] Hi, how would you discover the information described in subject on a Linux OS? I think that parsing /proc/cpuinfo can give much of the information, but not all. For example, if I have a Quad Core processor,... Posted: 2010-03-09 02:02:44 | cache, cachesize |
| How are caches updated on write?[Forums] Hello, As far I know, when a processor wants to store a value to some memory location, the value is stored to the processor's cache, and then populated to actual RAM. This way the value is also automatically... Posted: 2010-03-07 12:28:13 | cache, cache coherence, multi-core |
| Application's threads layout -- optimal binding of threads to CPUs (cores)[Forums] I'm looking for general rules of how threads should be assigned (affinitized) to processing units. Even that I can't use any scientific background, I think I can safely state, that when a high performance,... Posted: 2009-09-23 01:59:26 | Affinity-mask, cache, multi core, NUMA |
| Performance Monitoring: Instruction cache[Forums] Hi everybody,I'm a newbie, and its my first post here, so hope this is the right forum for asking my question (apologize if its wrong forum...)I am performing some performance monitoring on my Intel Core... Posted: 2009-09-23 01:10:56 | cache, Performance Monitoring |
| Cost of IPI (inter-processor interrupt) ?[Forums] Dear forum contributors,what is the cost of IPI? As far I know, inter-processor interrupts are used to synchronize cache between cores and processors. Such synchronization can be "costly" (my state of... Posted: 2009-09-18 08:01:32 | cache, cache blocking, Contention, ipi |
| clflush over the LAPIC mapping[Forums] I am remapping the LAPIC registers page to some virtual address. During the remap procedure, virtual memory subsystem invalidates the TLB for the page and then does clflush over the region, looping from... Posted: 2009-09-14 07:49:56 | cache, SSE2 |
| determining L1 and L2 cache state[Forums] I apologize in advance if this has already been covered, but I'm trying to get worst case timing of some section of code and this requires all of L1 (data) and L2 cache to be dirty; of course L1 instruction... Posted: 2009-08-25 10:00:48 | cache |
| Recognizing Efficient Use of Caches in Code for the Itanium® Processor Family[Knowledgebase] by Joseph Bissell, University of Delawareand Walt Triebel, Fairleigh Dickinson University(Adapted from original material authored by Rick Booth) Introduction To achieve optimal performance from processors... Posted: 2009-02-20 00:00:00 by bissell | cache, coding |
| Intel® Virtualization Developer Community[Knowledgebase] The Virtualization community makes it easy to understand, discover uses for, enable and identify opportunities for your virtualization solutions, and share with others in the Community. Developers,... Posted: 2009-11-09 00:00:00 by Roger Herrick Jr (Intel) | cache, EP Efficient Performance, EPT Extended Page Tables, FlexPriority, page tables, QPI Quick Path Interconnect, TXT Trusted Execution Technology, VMDq Virtual machine Device Queues, VMM Virtual Machine Monitor, VT-c, VT-D, VT-x |