How-To
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|---|---|
| How to Apply Application-Level Tuning on the ASP.NET Platform [Knowledgebase] Challenge Apply application-level tuning to a hypothetical ASP.NET* application. After system-level bottlenecks have been alleviated, developers can further increase performance through changes i ... Posted: 2009-03-03 16:15:14 by | .net, How-To |
| How to Apply System-Level Tuning on the ASP.NET Platform [Knowledgebase] Challenge Apply system-level tuning to a hypothetical ASP.NET application. Consider a hypothetical workload, designed to provide a representative yet simple Web application, exercising most of th ... Posted: 2009-03-03 16:17:20 by | .net, How-To |
| How to Compile .java Files into .Net Executables [Knowledgebase] Challenge Create a .NET executable from Java* source code. Microsoft Visual J# .NET* includes an implementation of many Java Development Kit (JDK) 1.1.4* packages, including the Abstract Windowin ... Posted: 2008-11-25 14:00:35 by | .net, How-To |
| How to Convert Java .class Files to .NET Executables [Knowledgebase] Challenge Execute compiled Java files under .NET without having access to the Java source code. For the sake of this example, assume that the following Java files have been compiled using a nativ ... Posted: 2009-03-03 16:23:41 by | .net, How-To |
| How to Create & Version a .NET Assembly [Knowledgebase] Challenge Create a .NET assembly and manage its version numbering. An assembly is a "logical DLL." It can comprise one or more physical files (which typically use the DLL suffix). An assembly con ... Posted: 2008-11-25 14:10:53 by | .net, How-To |
| How to Inspect the Internal Structure of a .NET Executable [Knowledgebase] Challenge Analyze a .NET executable to identify dependencies upon other assemblies.The executable in this example was created from Java .class files using the Jblmp utility; the procedure for doi ... Posted: 2009-03-03 16:28:12 by | .net, How-To |
| How to Tune the MACHINE.CONFIG File on the ASP.NET Platform [Knowledgebase] Challenge Tune the machine.config file to optimize performance of an ASP.NET application. There are a number of ASP.NET settings that reside in the machine.config file provided with the .NET* Fra ... Posted: 2009-03-03 16:32:30 by | .net, How-To |
| How to Use a .NET Assembly [Knowledgebase] Challenge Use a .NET assembly. The following code shows a test application that exercises the CakeInfo assembly that was created in the separate item, "How to Create & Version a .NET Assembly ... Posted: 2008-11-25 16:04:39 by | .net, How-To |
| Optimize Applications on the ASP.NET Platform [Knowledgebase] Challenge Optimize an ASP.NET application. The goal of applying optimizations is typically to achieve maximum throughput and/or to lower response time. Optimizing a complex system consisting of a ... Posted: 2009-03-09 14:25:10 by | .net, How-To |
| Send Email from an ASP .NET Environment [Knowledgebase] by Rahul Guha Challenge Sending email from ASP .NET pages has become a very typical request. In pre-.NET days one had to make use of a COM component (usually CDO or CDONTS), which allowed the de ... Posted: 2009-03-10 16:30:42 by | .net, How-To |
| Schedule Exclusive Access [Knowledgebase] This document is intended to assist users of the Intel® Remote Access service. This guide provides instructions on requesting an Exclusive Access remote Software Development Vehicle (SDV). Developer ... Posted: 2009-03-10 15:18:53 by | Access to upcoming processors, How-To |
| Initiate a Microsoft RTC Session in Windows XP [Knowledgebase] Challenge Use Microsoft's real-time communication (RTC) API to enable an application to initiate a communication session with another participant. The RTC API enables developers to enhance the co ... Posted: 2008-11-25 16:55:19 by | Design superior apps, How-To |
| Integrate Real-Time Communications in Windows XP [Knowledgebase] Challenge Integrate rich-client communications into Microsoft Windows* XP applications. This functionality includes the building blocks to add instant messaging, voice and video-conferencing, and ... Posted: 2008-11-26 09:44:59 by | Design superior apps, How-To |
| Prepare for a Microsoft RTC Session in Windows XP [Knowledgebase] Challenge Prepare an application to initiate a communication session using Microsoft's real-time communication (RTC) API. The RTC API enables developers to enhance the communication capabilities ... Posted: 2008-12-04 13:35:50 by | Design superior apps, How-To |
| Process Microsoft RTC Session Data in Windows XP [Knowledgebase] Challenge Enable an application to process real-time streaming session data generated using Microsoft's real-time communication (RTC) API. The RTC API enables developers to enhance the communicat ... Posted: 2008-12-05 08:13:42 by | Design superior apps, How-To |
| Avoid Bottlenecks in Simple Math Functions [Knowledgebase] Challenge Avoid bottlenecks associated with simple math functions in a wide variety of floating-point applications, ranging from financial analytics to 2D image manipulation to 3D physics engines ... Posted: 2009-02-26 20:49:45 by | Develop for Core processor, Algorithm Coding, How-To |
| Explicit Prototyping for Floating-Point Functions [Knowledgebase] Challenge Avoid consumption of duplicate resources and corrupted parameters associated with the lack of explicit prototyping in the use of floating-point functions for the Itanium® processor arc ... Posted: 2008-11-24 15:52:07 by | Develop for Core processor, Algorithm Coding, How-To |
| Implement Software Exception Handling [Knowledgebase] Challenge Implement software exception handling for the Intel® C++ Compiler that is compliant with the Microsoft* Structured Exception Handling (SEH) implementation. There are, in general, two t ... Posted: 2009-03-04 13:46:07 by | Develop for Core processor, Algorithm Coding, How-To |
| Learn the 10 Most Important Technologies [Knowledgebase] Introduction When we told our readers what technologies they needed to learn, they told us: "Easier said than done." While that's true, there is an approach to learning that can make it eas ... Posted: 2009-03-05 10:35:38 by | Develop for Core processor, Algorithm Coding, How-To |
| Sound Coding Practices (Things to Avoid) [Knowledgebase] Challenge Establish standard coding practices in terms of things to avoid (as opposed to desirable actions, which are covered in a separate item, identified below). Solution Make the follow ... Posted: 2009-03-10 17:23:42 by | Develop for Core processor, Algorithm Coding, How-To |
| Use Explicit Prototyping [Knowledgebase] Challenge Avoid limitations due to the requirement in ANSI C that parameters be passed as either intor doubleif functions are not protoyped. Passing parameters as either int or double might be in ... Posted: 2009-03-11 17:01:15 by | Develop for Core processor, Algorithm Coding, How-To |
| Support the CONTEXT Structure in Windows 2000 (64-bit) [Knowledgebase] Challenge Provide support for the CONTEXT structure on both 32-bit Windows and 64-bit Windows operating systems. Windows 2000 (64-bit) uses CONTEXT structures to perform various internal operatio ... Posted: 2009-03-11 09:45:32 by | coding, Develop for Core processor, How-To |
| Vectorize Code Using C/C++ Classes on 32-Bit Intel® Architecture [Knowledgebase] Challenge Vectorize code by means of C++ vector classes. Consider the following simple loop: void add(float *a, float *b, float *c) { int i; for (i = 0; i < 4; i++) { c[i] = a[i] ... Posted: 2009-01-26 15:07:17 by | coding, Develop for Core processor, How-To |
| Avoid Partial Memory Accesses on 32-Bit Intel® Architecture [Knowledgebase] Challenge Avoid partial memory accesses. Consider a case with large load after a series of small stores to the same area of memory (beginning at memory address mem). The large load will stall in ... Posted: 2009-03-02 08:58:14 by | data, Develop for Core processor, How-To |
| Correct Endian Issues with Hex Constants Used as Byte Arrays [Knowledgebase] Challenge Modify code that includes hex constants used as byte arrays written for big-endian systems to run properly on Intel® architecture. Endianness refers to how a data element and its indiv ... Posted: 2008-11-21 14:08:12 by | data, Develop for Core processor, How-To |
| Loop Blocking to Optimize Memory Use on 32-Bit Architecture [Knowledgebase] Challenge Improve memory utilization by means of loop blocking. The main purpose of loop blocking is to eliminate as many cache misses as possible. Consider the following loop, as it exists befor ... Posted: 2009-03-06 08:26:12 by | data, Develop for Core processor, How-To |
| Manage Structure Padding to Avoid Data Bloat [Knowledgebase] Challenge Reduce or eliminate data bloat due to structure padding. With the Itanium® architecture, data boundaries are naturally aligned, instead of freely (any-byte) aligned as on 32-bit Inte ... Posted: 2009-03-09 09:37:38 by | data, Develop for Core processor, How-To |
| Manipulate Data Structure to Optimize Memory Use on 32-Bit Architecture [Knowledgebase] Challenge Improve memory utilization by manipulating data-structure layout. For certain algorithms, like 3D transformations and lighting, there are two basic ways of arranging the vertex data. Th ... Posted: 2009-03-09 10:38:24 by | data, Develop for Core processor, How-To |
| Manipulate Data Structure to Optimize Memory Use on 32-Bit Intel® Architecture [Knowledgebase] Challenge Improve memory utilization by manipulating data-structure layout. For certain algorithms, like 3D transformations and lighting, there are two basic ways of arranging the vertex data. Th ... Posted: 2008-12-02 09:12:14 by | data, Develop for Core processor, How-To |
| Replace a Set of Pointers With a Base Pointer to Reduce Data Bloat [Knowledgebase] Challenge Reduce data bloat due to the use of many pointers. Pointers in the Itanium® architecture are twice the size of pointers in 32-bit Intel® architecture, which may effectively double the ... Posted: 2008-12-05 13:11:27 by | data, Develop for Core processor, How-To |
| Become Familiar with Streaming SIMD Extensions 3 Instructions [Knowledgebase] Challenge Become familiar with SSE3 Instructions. SSE3 for the 32-bit Intel® architecture is a set of 13 new instructions that accelerate performance of Streaming SIMD Extensions (SSE) technolog ... Posted: 2009-03-02 09:42:42 by | Develop for Core processor, Instructions, How-To |
| Implement a Horizontal Add/Subtract with SSE3 Instructions [Knowledgebase] Challenge Implement a horizontal add/subtract using SSE3 instructions. Most SIMD instructions operate vertically. Data elements of the result in position k are a function of data elements in posi ... Posted: 2009-03-03 16:49:35 by | Develop for Core processor, Instructions, How-To |
| Implement ADDSUBxx Streaming SIMD Extensions 3 Instructions [Knowledgebase] Challenge Implement SSE3 single-precision and double-precision packed ADDSUBxx instructions. ADDSUBPS has two 128-bit operands. The instruction performs single-precision addition on the second ... Posted: 2009-03-03 16:45:42 by | Develop for Core processor, Instructions, How-To |
| Implement Application Programming Model for Streaming SIMD Extensions 3 Instructions [Knowledgebase] Challenge Implement the application-programming model for SSE3 Instructions. The application-programming environment for using SSE3 instructions is unchanged from that provided for Streaming SIMD ... Posted: 2009-03-04 08:31:25 by | Develop for Core processor, Instructions, How-To |
| Implement Streaming SIMD Extensions 3 Instructions Data-Movement Instructions [Knowledgebase] Challenge Implement SSE3 data-movement instructions. MOVSHDUP loads/moves 128-bits, duplicating the second and fourth 32-bit data elements. MOVSLDUP loads/moves 128-bits, duplicating the first an ... Posted: 2009-03-05 08:07:32 by | Develop for Core processor, Instructions, How-To |
| Implement the FISTTP Streaming SIMD Extensions 3 Instruction [Knowledgebase] Challenge Implement the SSE3 FISTTP instruction. FISTTP (Store Integer and Pop from x87-FP with Truncation) behaves like the FISTP instruction but uses truncation, irrespective of the rounding mo ... Posted: 2009-03-05 08:11:44 by | Develop for Core processor, Instructions, How-To |
| Satisfy the System Programming Model for Streaming SIMD Extensions 3 Instructions [Knowledgebase] Challenge Satisfy system-programming model and requirements for SSE3 instructions. The SSE3 Instructions state requires no new OS support for saving and restoring the new state during a context s ... Posted: 2009-03-10 15:13:14 by | Develop for Core processor, Instructions, How-To |
| Switch between Instruction Types on 32-Bit Intel® Architecture [Knowledgebase] Challenge Switch between using 64-bit SIMD integer instructions and x87 floating-point instructions. All 64-bit SIMD integer instructions use the MMX™ technology registers, which share register ... Posted: 2009-03-11 10:27:41 by | Develop for Core processor, Instructions, How-To |
| Vectorize Code Using Intrinsics on 32-Bit Intel® Architecture [Knowledgebase] Challenge Vectorize code by means of intrinsics. Intrinsics provide the access to the ISA functionality using C/C++ style coding instead of assembly language. Consider the following simple loop: ... Posted: 2008-11-14 14:26:20 by | Develop for Core processor, Instructions, How-To |
| Create a UNIX (including Linux) Shared Library [Knowledgebase] Challenge Create a UNIX shared library based on a piece of existing code. For example, the following code calculates how many people can be fed by a particular size of birthday cake. The feeds_ho ... Posted: 2008-11-24 12:44:57 by | libraries, Develop for Core processor, How-To |
| Implement the LibM Math Library [Knowledgebase] Challenge Implement the LibM Math Library. The LibM library provides highly optimized scalar math functions that serve as direct replacements for the standard C calls. The LibM versions are fully ... Posted: 2009-03-05 08:17:16 by | libraries, Develop for Core processor, How-To |
| Implement the Short Vector Math Library [Knowledgebase] Challenge Implement the Intel® Short Vector Math Library (SVML). The SVML leverages SSE & SSE2 instructions to process either four packed single-precision numbers or two packed double-precis ... Posted: 2009-03-05 08:25:48 by | libraries, Develop for Core processor, How-To |
| Install a UNIX (including Linux) Shared Library [Knowledgebase] Challenge Install a UNIX shared library prior to use. The shared-library file, once created, should be copied to one of the standard library directories. Creating such a file, libcakeinfo.so.1.0, ... Posted: 2008-11-26 09:36:53 by | libraries, Develop for Core processor, How-To |
| Link your Project to MKL libraries [Knowledgebase] Introduction How to link your project to MKL libraries, linking tips for MKL libraries, and Intel® Math Kernel Library compiler issues. Math Kernel Library (MKL) - Overview Just Link In To ... Posted: 2009-03-05 10:56:35 by | libraries, Develop for Core processor, How-To |
| Manage Versioning, Libraries, & Assemblies in Windows versus UNIX (including Linux) [Knowledgebase] Challenge Create libraries of commonly used functionality, freeing application developers from having to repeatedly write the same code time and again.The types of libraries available and the mec ... Posted: 2008-12-02 08:23:20 by | libraries, Develop for Core processor, How-To |
| Update a UNIX (including Linux) Shared Library [Knowledgebase] Challenge After updating a UNIX shared library, increment the version number to reflect the change. A library can be modified, and depending on the nature of the change, applications can pick up ... Posted: 2009-03-11 14:34:44 by | libraries, Develop for Core processor, How-To |
| Use and Locate a UNIX (including Linux) Shared Library [Knowledgebase] Challenge Use and locate a UNIX shared library. The caketester application in the following code shows an example that tests the libcakeinfo library that is created in a separate item, "Create a ... Posted: 2009-01-09 09:57:23 by | libraries, Develop for Core processor, How-To |
| Use Intriniscs [Knowledgebase] by Joseph D. Wieber, Jr and Gary M. Zoppetti Introduction In "Introduction to Intrinsics," we introduced the intrinsics provided by the Intel® C++ Compiler. Intrinsics allow a programmer to uti ... Posted: 2008-12-09 08:29:33 by | libraries, Develop for Core processor, How-To |
| Determine the Correct Interconnect Technology for an HPC Cluster [Knowledgebase] Challenge Determine the type of interconnect technology required for a particular High-Performance Computing (HPC) cluster. The typical choices for cluster networking today are: 100BASE Fast ... Posted: 2009-03-02 14:19:46 by | High performance computing, How-To |
| Determining whether HPC Cluster Should Be 32-Bit or 64-Bit Processors [Knowledgebase] Challenge Determine whether a High-Performance Computing (HPC) cluster should be based on 32-bit machines or 64-bit machines. HPC clusters are a form of parallel computing hardware. Parallel hard ... Posted: 2009-03-02 14:28:45 by | High performance computing, How-To |
| Access a 32-Bit DLL from a Native 64-Bit Process on Intel Architecture [Knowledgebase] Challenge Access an IA-32 DLL from a native Intel® Itanium® architecture Process. Porting an application to the Itanium architecture has many benefits, including the ability to take advantage o ... Posted: 2009-07-08 12:38:37 by | itanium, 64-bit Coding, How-To |
| Avoid Memory-Coding Errors on 64-Bit Intel® Architecture [Knowledgebase] Challenge Avoid performance and security issues associated with memory-coding errors. Memory-coding errors lead directly to security vulnerabilities. Memory-access miscodings appear to be respons ... Posted: 2008-11-19 16:44:01 by | itanium, 64-bit Coding, How-To |
| Ensure that the 64-Bit Compiler Can Find Type Mismatches [Knowledgebase] Challenge Avoid type-mismatch errors due to the use of #define to define constants with the 64-bit Intel® architecture. In the following code, where #define is used for a constant, the compiler ... Posted: 2008-11-24 15:24:34 by | itanium, 64-bit Coding, How-To |
| Handle Win64 Errors Related to Obsolete Win32 Constants [Knowledgebase] Challenge Address Win64* compilation errors related to old Win32* constants. A few of the constants used with the Win32 APIs have been modified for Win64; as a result, using the old constants wil ... Posted: 2008-11-25 10:58:38 by | itanium, 64-bit Coding, How-To |
| Handle Win64 printf or wsprintf Warnings [Knowledgebase] Challenge Address Win64* compilation warnings related to improper use of Win64 printf or wsprintf format specifiers. Using improper format specifiers in printf or wsprintf will generate warnings. ... Posted: 2008-11-25 12:37:56 by | itanium, 64-bit Coding, How-To |
| Handle Win64 Truncation Warnings [Knowledgebase] Challenge Address Win64* compilation warnings related to truncation. Most of the warnings that you encounter when compiling for Win64 are truncation-related warnings (conversion from INT64 to int ... Posted: 2008-11-25 12:56:44 by | itanium, 64-bit Coding, How-To |
| Manage Thread-Stack Size in 64-bit UNIX [Knowledgebase] Challenge Determine the default thread-stack size for a particular implementation of UNIX and adjust that size in your application. The operating system permits multiple threads of execution with ... Posted: 2009-03-09 09:43:15 by | itanium, 64-bit Coding, How-To |
| Manage Thread-Stack Size in Windows 2000 (64-bit) [Knowledgebase] Challenge Automatically allocate stack space in Windows 2000 (64-bit) applications to avoid stack overflow. The operating system permits multiple threads of execution within a process's address s ... Posted: 2009-03-09 09:51:45 by | itanium, 64-bit Coding, How-To |
| Select a Win64 Porting Model [Knowledgebase] Challenge Choose the appropriate model for porting an application from the Win32 environment to Win64. Win64 provides four different porting options. The correct option for a given application de ... Posted: 2009-03-10 15:58:57 by | itanium, 64-bit Coding, How-To |
| Support Hex Constants on 64-Bit Intel Architecture [Knowledgebase] Challenge Modify code to support the use of integer-constant-type suffixes on 64-bit Intel® architecture. If a piece of code uses hex constants to generate a particular value, you might need to ... Posted: 2009-03-11 09:33:22 by | itanium, 64-bit Coding, How-To |
| Use Appropriate Data Types to Manage 64-bit Data Size [Knowledgebase] Challenge Ensure that you are using 32-bit or 64-bit data types as appropriate for your variables. Caution in this area conserves resources and avoids data bloat. Solution If a variable wil ... Posted: 2009-03-11 16:50:54 by | itanium, 64-bit Coding, How-To |
| Use Make files to Resolve Win64 Porting Issues [Knowledgebase] Challenge Identify issues associated with porting an application to the Win64 environment. Once an appropriate model has been chosen for porting an application to the Win64 environment, which is ... Posted: 2009-03-11 17:41:08 by | itanium, 64-bit Coding, How-To |
| Guide Compilers to Optimize Inner Loops for 64-Bit Intel Architecture [Knowledgebase] Challenge Guide the compiler to perform the proper amount of optimization on an inner loop. One of the quickest ways to find an inner loop in an assembly language listing is to look for sections ... Posted: 2009-03-03 15:55:07 by | itanium, How-To, compiler |
| Improve Performance on 64-Bit Intel Architecture with Intel C++ Compiler for Linux Options [Knowledgebase] Challenge Use the options built into the Intel® C++ Compiler for Linux to improve performance on the Itanium® processor. The Intel compilers have robust feature sets to support optimization at ... Posted: 2009-01-26 15:46:32 by | itanium, How-To, compiler |
| Resolve Cache Misses on 64-Bit Intel Architecture [Knowledgebase] Challenge Resolve cache misses that cause a significant number of stall cycles. These occur when data is not in the desired cache and data retrieval requires access to a slower cache, memory, or ... Posted: 2009-03-10 13:39:24 by | itanium, How-To, compiler |
| Use Intel Compilers Successfully for 64-Bit Intel Architecture [Knowledgebase] Challenge Use the Intel® Compilers for maximum performance. This item answers common questions about using the Intel compilers, and it also gives troubleshooting and optimization techniques. ... Posted: 2009-03-11 17:11:32 by | itanium, How-To, compiler |
| Use Pragmas with the Intel® C++ Compiler for Linux on 64-Bit Architecture [Knowledgebase] Challenge Use pragmas with the Intel® C++ Compiler for Linux to improve performance on the Itanium® processor. A pragma is a statement used to suggest that a compiler optimization be performed ... Posted: 2009-01-26 16:06:11 by | itanium, How-To, compiler |
| Allocate Memory Optimally to the Bufferpool and Sortheap for DB2 Databases on Itanium-Based Systems [Knowledgebase] Challenge Allocate memory to the bufferpool and sortheap for high performance of IBM DB2* databases on Itanium®-based systems. DB2 allocates memory mainly on the logical-node level for bufferpoo ... Posted: 2009-03-01 22:02:48 by | itanium, DB2, How-To |
| Configure Striping Size and Eventsize for IBM DB2 Databases on Itanium-Based Systems [Knowledgebase] Challenge Configure striping size and eventsize for IBM DB2* Databases to produce high performance on Itanium®-based systems. The organization of data on the disks is an important factor for ben ... Posted: 2009-03-02 12:50:57 by | itanium, DB2, How-To |
| Optimally Define IBM DB2 Bufferpool Page Size for Itanium-Based Systems [Knowledgebase] Challenge Define bufferpool size for IBM DB2 databases to produce high performance on Itanium®-based systems. Controlling the size of the bufferpool pages is a key performance-tuning measure. A ... Posted: 2009-03-09 14:22:42 by | itanium, DB2, How-To |
| Develop Coding Best Practices Targeting Compilers for 64-Bit Intel® Architecture [Knowledgebase] Challenge Write code that makes the best use of the compiler's capabilities for 64-bit Intel® architecture. In addition to implementation-specific optimizations, coding practices that target com ... Posted: 2009-03-02 14:53:59 by | itanium, Itanium Coding, How-To |
| Implement Efficient MADD Operations on 64-Bit Intel Architecture [Knowledgebase] Challenge Implement a multiply and add operation efficiently on 64-bit Intel® architecture. Integer matrix multiplication is a common procedure that is used generically to explore options for op ... Posted: 2009-03-04 08:45:56 by | itanium, Itanium Coding, How-To |
| Include Optimized Assembly Code in Compilation for 64-Bit Intel® Architecture [Knowledgebase] Challenge Include assembly code in compilation and determine its effectiveness. Once you have optimized assembly code by hand, you must include that optimized assembly in the compilation and then ... Posted: 2009-03-05 09:25:07 by | itanium, Itanium Coding, How-To |
| Locate Code in Assembly Language for 64-Bit Intel® Architecture [Knowledgebase] Challenge Locate code in an assembly language listing that corresponds to a specific passage of source code. The importance of interpreting compiler-produced assembly language code is the fact th ... Posted: 2009-03-06 08:17:03 by | itanium, Itanium Coding, How-To |
| Manage Jump Buffer Size for Itanium Architecture [Knowledgebase] Challenge Manually allocate a jump buffer to ensure that it has adequate space to accommodate sufficient pointers for Itanium® architecture. When using a non-ANSI-defined jmp_buf data type, code ... Posted: 2009-03-06 09:00:49 by | itanium, Itanium Coding, How-To |
| Support Integer-Constant-Type Suffixes on 64-Bit Architecture [Knowledgebase] Challenge Modify code to support the use of integer-constant-type suffixes on 64-bit Intel® architecture. If integer-constant-type suffixes are used in the code, you might need to modify the cod ... Posted: 2009-03-11 09:40:13 by | itanium, Itanium Coding, How-To |
| Trace the Logic in an Assembly Code Listing for 64-Bit Intel Architecture [Knowledgebase] Challenge Analyze compiler-generated assembly language to determine the logic of critical sections of code. A structured methodology for gaining an understanding of the assembly code is essential ... Posted: 2009-03-11 11:52:10 by | itanium, Itanium Coding, How-To |
| Use Code from the Intel® Itanium Processor on the Itanium 2 Processor [Knowledgebase] Challenge Get better performance when moving an application written for the Intel® Itanium® processor to the Itanium® 2 processor. The second-generation Itanium processor, the Itanium 2 proces ... Posted: 2009-03-11 16:55:17 by | itanium, Itanium Coding, How-To |
| Use Code Guards to Compile 32-bit Code for the Itanium Architecture [Knowledgebase] Challenge Designate specific blocks of 32-bit code to be compiled for the Itanium® architecture. Source code often needs local customization based on the target platform. Solution Use code ... Posted: 2009-03-11 16:59:49 by | itanium, Itanium Coding, How-To |
| Use Intel Performance Libraries on 64-Bit Architecture [Knowledgebase] Challenge Implement code form Intel® Performance Libraries to optimize code associated with hotspots for the 64-bit Intel® architecture. Intel has developed highly optimized standardized routin ... Posted: 2009-03-11 17:28:30 by | itanium, libraries, How-To |
| Ensure Accurate Data Access When Using An Offset with Itanium Architecture [Knowledgebase] Challenge Avoid misidentifying data fields due to hard-coded offsets being used to access data structures with Itanium® architecture. The following code contains a hard-coded offset to access ... Posted: 2009-03-02 15:50:56 by | itanium, Memory Access, How-To |
| Identify Bank/Address Conflicts on 64-Bit Intel Architecture [Knowledgebase] Challenge Identify and locate conflicts in the EXE pipeline. Microprocessor cache architectures frequently have access structures that allow for very low latencies, but in some circumstances, thi ... Posted: 2009-03-03 16:42:43 by | itanium, Memory Access, How-To |
| Quantify Integer Bank-Conflict Penalties on 64-Bit Intel Architecture [Knowledgebase] Challenge Measure the performance penalty associated with L2 bank conflicts on integer-data loads. Access to cacheable integer data always goes through the L1D cache. This complicates the issue o ... Posted: 2009-03-10 11:12:21 by | itanium, Memory Access, How-To |
| Remove Many Bank Conflicts on 64-Bit Intel® Architecture [Knowledgebase] Challenge Remove bank conflicts from high-level loops. Removing bank conflicts is, in many cases, rather simple. Consider the following double-precision matrix multiply in Fortran: Do k= ... Posted: 2009-03-10 11:53:42 by | itanium, Memory Access, How-To |
| Resolve Address Conflicts on 64-Bit Architecture [Knowledgebase] Challenge Resolve address conflicts that cause a significant number of stall cycles. Cache misses occur when data is not in the desired cache and data retrieval requires access to a slower cache, ... Posted: 2009-03-10 13:33:41 by | itanium, Memory Access, How-To |
| Resolve Data-Alignment Errors for the Itanium Architecture [Knowledgebase] Challenge Avoid program exceptions associated with misaligned data objects in the 64-bit Intel® architecture. Under both Linux* and Win64*, developers will often encounter data-alignment errors ... Posted: 2009-03-10 13:43:53 by | itanium, Memory Access, How-To |
| Short Data Segment Overflow Errors on 64-Bit Architecture [Knowledgebase] Challenge Solve a potential short data segment overflow link error on Intel® Itanium® Architecture on Linux* 64 platforms when building very large static images. This problem exists on Windows* ... Posted: 2009-01-27 16:09:44 by | itanium, Memory Access, How-To |
| Analyze Memory Accesses on 64-Bit Intel Architecture [Knowledgebase] Challenge Determine what memory accesses are causing EXE pipeline stalls accumulated by the BE_EXE_Bubble counter. Most memory-access stall cycles are accumulated by the BE_EXE_Bubble counter. Th ... Posted: 2009-03-01 22:13:26 by | itanium, performance, How-To |
| Code Timing and Profiling for Linux on 64-Bit Intel® Architecture [Knowledgebase] Challenge Measure the time a program and its functions take to execute as part of the diagnosis phase of performance optimization. Such measurements are extremely valuable as a simple means to be ... Posted: 2009-03-02 12:44:28 by | itanium, performance, How-To |
| Develop an Execution-Time Benchmark on 64-Bit Intel Architecture [Knowledgebase] Challenge Develop a benchmark to measure the execution time of the piece of code you are optimizing. This is essential to determine whether your code changes are helping or hurting performance. M ... Posted: 2009-03-02 14:48:42 by | itanium, performance, How-To |
| Handle Streaming Data Optimally on 64-Bit Architecture [Knowledgebase] Challenge Handle long, high-bandwidth data streams optimally with the Intel® Itanium® processor. Proper utilization of the lfetch instructions is vital to optimal handling of streaming data. ... Posted: 2009-03-03 15:58:05 by | itanium, performance, How-To |
| Identify Back-End Bubbles on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify a processor back-end bubble on the Intel® Itanium® processor. A 'bubble' is defined as any delay in the processor. The 'back end' is the place where instructions are retired ... Posted: 2008-11-25 16:16:39 by | itanium, performance, How-To |
| Improve Code Based on Root-Cause Analysis on 64-Bit Intel® Architecture [Knowledgebase] Challenge Improve the efficiency of code based on root-cause analysis of back-end bubbles. That analysis is covered in a separate item How to Perform Back-End Bubble Root-Cause Analysis on 64-Bit ... Posted: 2008-11-25 16:26:53 by | itanium, performance, How-To |
| Improve Performance on 64-Bit Architecture of Applications with Many Small Functions [Knowledgebase] Challenge Improve application performance in programs that contain many frequently used small to medium-sized functions. This characteristic is very common in object-oriented C++ programs that im ... Posted: 2009-03-05 09:14:06 by | itanium, performance, How-To |
| Increase the Frequency of First-Level Instruction-Cache Hits on 64-Bit Intel Architecture [Knowledgebase] Challenge Increase the frequency with which the first-level instruction cache (L1D) is a hit for integer data. This optimization is key to achieving good performance on the Intel® Itanium® proc ... Posted: 2009-03-05 09:29:50 by | itanium, performance, How-To |
| Instruction Latencies in Assembly Code for 64-Bit Intel® Architecture [Knowledgebase] Challenge Optimize assembly-language code for the Itanium® processor family in terms of instruction latencies. The latency of an instruction is the length of time that has elapsed from when the ... Posted: 2009-03-05 09:39:07 by | itanium, performance, How-To |
| Perform Back-End Bubble Root-Cause Analysis on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify the root cause of a back-end processor bubble on the Intel® Itanium® processor. A separate item, How to Identify Back-End Bubbles on 64-Bit Intel® Architecture, shows how to ... Posted: 2009-01-16 10:55:45 by | itanium, performance, How-To |
| Perform Code Timing and Profiling for Linux on 64-Bit Architecture [Knowledgebase] Challenge Measure the time a program and its functions take to execute as part of the diagnosis phase of performance optimization. Such measurements are extremely valuable as a simple means to be ... Posted: 2009-01-26 15:58:59 by | itanium, performance, How-To |
| Prepare Applications for Optimization on 64-Bit Intel® Architecture [Knowledgebase] Challenge Prepare applications for optimization on the Intel® Itanium® processor family. The first issue in getting high performance code on Itanium-based systems is to get the code ported or w ... Posted: 2009-03-09 17:30:01 by | itanium, performance, How-To |
| Prioritize Bottlenecks on the Itanium Processor [Knowledgebase] Challenge Prioritize Performance Bottlenecks in terms of their impact on performance to support their resolution in order of importance. The key to optimizing an application is to use performance ... Posted: 2009-03-09 17:40:57 by | itanium, performance, How-To |
| Quantify Floating-Point Bank-Conflict Penalties on 64-Bit Intel Architecture [Knowledgebase] Challenge Measure the performance penalty associated with bank conflicts on floating-point loads. If you are dealing with a looping algorithm and have unrolled the loops (or if the compiler has d ... Posted: 2009-03-10 11:03:29 by | itanium, performance, How-To |
| Quantify the Penalty of Branch Misprediction on 64-Bit Architecture [Knowledgebase] Challenge Determine the performance penalty associated with the misprediction of a conditional branch on a processor based on 64-bit Intel® architecture. A separate item, How to Identify Branch ... Posted: 2009-02-27 10:11:36 by | itanium, performance, How-To |
| Resolve Back-End Bubbles on 64-Bit Intel® Architecture [Knowledgebase] Challenge Identify back-end bubbles (processor delays) in 64-bit applications and resolve them. Like any hardware platform, the Intel® Itanium® processor is dependent for performance upon the q ... Posted: 2008-12-05 13:22:18 by | itanium, performance, How-To |
| Schedule Instructions Optimally on 64-Bit Intel® Architecture [Knowledgebase] Challenge Schedule instructions properly for optimal performance on the Intel® Itanium® processor. Optimal scheduling will minimize the chances of implicit stops or unexpected dispersal-related ... Posted: 2009-03-10 15:21:56 by | itanium, performance, How-To |
| Develop Linux Applications for Compatibility between Itanium-Based Systems and the IBM POWER architecture [Knowledgebase] Challenge Help to ensure that Linux applications under development are cross-compatible between Itanium®-based systems and the IBM POWER* architecture. Solution Write endian-neutral code, ... Posted: 2009-03-02 14:58:22 by | itanium, Porting, How-To |
| Port Linux Applications [Knowledgebase] by Stephen Satchell How to Port Linux* Applications Porting your Linux* applications to the Itanium® architecture can be straightforward if you follow these suggestions, which highlight the key ... Posted: 2009-03-09 17:15:07 by | itanium, Porting, How-To |
| Analyze Bottlenecks from 64-bit Pipeline Stalls at the DET Stage [Knowledgebase] Challenge Identify dominant sources of performance bottlenecks accumulated by the BE_L1D_FPU_Bubble event, which accumulates stall cycles caused by the micropipelines associated with the L1D and ... Posted: 2008-11-19 15:08:13 by | itanium, Stall Analysis, How-To |
| Analyze Pipeline Flush Losses on 64-Bit Intel Architecture [Knowledgebase] Challenge Determine the causes of cycles lost due to pipeline flushes, based on events accumulated by the BE_Flush_Bubble counter. These stalled cycles are comprised of the following: Branch ... Posted: 2009-03-01 22:19:02 by | itanium, Stall Analysis, How-To |
| Analyze Pipeline Stalls on 64-Bit Intel Architecture [Knowledgebase] Challenge Identify and categorize the causes of pipeline stalls for maximum performance on the Itanium® processor and Itanium® processor. The objective of microarchitectural optimization is to ... Posted: 2009-03-01 22:24:45 by | itanium, Stall Analysis, How-To |
| Characterize Application Performance with Stall Events on 64-Bit Architecture [Knowledgebase] Challenge Use front-end stall-cycle events and back-end stall-cycle events to characterize the performance of an application on the Intel® Itanium® Processor. The Itanium® 2 Processor separate ... Posted: 2009-03-02 12:35:55 by | itanium, Stall Analysis, How-To |
| Functional Unit Stalls on 64-Bit Intel® Architecture [Knowledgebase] Challenge Minimize inefficiencies due to functional-unit latency stalls. Computers require functional-unit latency stalls to ensure that results are computed correctly. In a chain of instructions ... Posted: 2009-03-03 15:29:29 by | itanium, Stall Analysis, How-To |
| Quantify Memory-Stall Penalties on 64-Bit Architecture [Knowledgebase] Challenge Determine memory-access stall penalties due to simple cache misses. Whenever a load instruction attempts to access data from a data cache array that does not contain the desired data, i ... Posted: 2009-03-10 11:18:53 by | itanium, Stall Analysis, How-To |
| Register-Stack Engine Stalls on 64-Bit Architecture [Knowledgebase] Challenge Identify the source of stall cycles due to invocation of the Register Stack Engine (RSE). There are 96 general registers used for the register stacks. A deep call stack or a call stack ... Posted: 2009-03-10 11:48:52 by | itanium, Stall Analysis, How-To |
| Resolve Memory Access Stalls on 64-Bit Intel® Architecture [Knowledgebase] Challenge Resolve memory access stalls in the EXE pipeline stage on 64-Bit Intel® Architecture. Memory access stalls occur when the data is not available in the caches as expected. The instructi ... Posted: 2009-03-10 13:56:17 by | itanium, Stall Analysis, How-To |
| Add Mobility Requirements to the Software Development Life Cycle [Knowledgebase] Challenge Identify business requirements that are specific to a mobilized application architecture. An architecture designed for mobile applications incorporates the use of portable computing dev ... Posted: 2009-01-30 13:41:35 by | Application development, How-To |
| Build Cross-Platform Mobilized Applications [Knowledgebase] Abstract Introducing the Mobile Reference Model series of tutorials, articles, and source code providing developers with everything they need to create cross-platform, mobilized software solution ... Posted: 2009-01-15 08:07:38 by | Application development, How-To |
| Business case for mobilized solutions [Knowledgebase] Challenge Address the business drivers and the challenges that enterprises face when deploying mobile applications. Technology for its own sake cannot justify the implementation of mobilized appl ... Posted: 2009-03-02 10:22:09 by | Application development, How-To |
| Determine the Scope of a Software Mobilization Project [Knowledgebase] Challenge Establish the scope of the effort to create a mobilized version of an existing application. A number of capabilities are required to support an environment in which computing devices ar ... Posted: 2009-01-30 13:50:21 by | Application development, How-To |
| Formulate a Business Case for Deploying Mobilized Solutions [Knowledgebase] Challenge Address the business drivers and the challenges that enterprises face when deploying mobile applications. Technology for its own sake cannot justify the implementation of mobilized appl ... Posted: 2009-03-03 15:22:00 by | Application development, How-To |
| Mobilize Software Applications [Knowledgebase] Challenge Benefit from the increasingly wide deployment of mobile computing, obtaining a competitive advantage by mobilizing software applications. Software vendors can no longer regard desktop s ... Posted: 2009-03-09 12:05:39 by | Application development, How-To |
| Use Intelligent Documents as Enterprise Front-Ends [Knowledgebase] Challenge Implement user-friendly, lightweight, mobilized front-ends for business systems. The technology should allow non-technical users to implement it for particular business needs, while als ... Posted: 2009-03-11 17:14:57 by | Application development, How-To |
| Looking For an API to Detect Radio Off Condition for Centrino WLANs [Knowledgebase] Challenge Looking for a proper programmatic way to detect a "Radio off" (HW button) condition for Centrino WLANs (Intel Pro/Wireless): Is there an official API available or a documented way to qu ... Posted: 2009-03-06 08:21:31 by | How to Store and Retrieve Data From Cookies, How-To |
| Mobile Power Management Tool [Knowledgebase] Question Is there any mobile power management tool available to force the CPU in various power management conditions such as HFM and LFM? Solution If you are a software developer and are ... Posted: 2009-03-09 11:44:50 by | How to Store and Retrieve Data From Cookies, How-To |
| Address Changes in Network State in Mobilized Software [Knowledgebase] Challenge Detect network-state changes in a mobilized software application, and adapt appropriately. Remaining productive outside the office is a challenge. Recent platform advances meet many of ... Posted: 2009-08-17 16:52:00 by | Network aware, How-To |
| Address Connectivity State in Mobilized Software [Knowledgebase] Challenge Enable a mobilized application to provide virtually the same user experience, regardless of connection status. Today, we can connect mobile notebooks to the Internet at tens of thousan ... Posted: 2009-11-02 11:05:03 by | Network aware, How-To |
| Changes in Effective Data-Transfer Rate in Mobilized .NET Applications [Knowledgebase] Challenge Detect changes in effective data-transfer rate in a mobilized .NET* application. If we can detect changes in the effective data rate between two endpoints, then users can subscribe to h ... Posted: 2009-03-02 10:52:29 by | Network aware, How-To |
| Changes in Target Machine Visibility in Mobilized .NET* Applications [Knowledgebase] Challenge Detect IPEndPoint visibility changes in a mobilized .NET* application. Application developers must ask two questions related to changes in the visibility of IPEndPoints: "How can I tell ... Posted: 2009-03-02 12:19:22 by | Network aware, How-To |
| Detect Internet Connectivity for a Handheld [Knowledgebase] Challenge Detect Internet connectivity on a handheld device using the .NET* Compact Framework. The .NET Compact Framework provides classes for this purpose. Solution Depending on the needs ... Posted: 2009-03-02 14:00:07 by | Network aware, How-To |
| Determine Target Machine Visibility in Mobilized .NET* Applications [Knowledgebase] Challenge Determine IPEndPoint visibility for a mobilized .NET* application. This is first question that we need to ask before transferring data to or from a remote system: "Is the service on my ... Posted: 2009-03-02 14:15:23 by | Network aware, How-To |
| Determine Which Connection a Mobilized Application Will Use [Knowledgebase] Challenge Determine which connection a mobilized application will use in a system configuration with multiple network adapters. The mobile platform may have multiple network connections at the sa ... Posted: 2009-03-02 14:24:14 by | Network aware, How-To |
| Effective Data-Transfer Rate in Mobilized .NET* Applications [Knowledgebase] Challenge Determine the effective data-transfer rate in a mobilized .NET* application. The effective data rate refers to the speed at which real data is being transferred to a remote IP Endpoint. ... Posted: 2009-03-02 15:26:08 by | Network aware, How-To |
| Monitor Network Connection Status Using .NET and Web Services [Knowledgebase] Challenge Determine whether a system is connected to the network, and monitor its status to determine when it reconnects or disconnects. Although the connection types and speeds vary considerably ... Posted: 2009-03-09 13:20:17 by | Network aware, How-To |
| Network Detection for Mobility [Knowledgebase] Challenge Implement robust support for network detection in mobilized software applications. A true mobility-enabled application must adapt to the changing network connectivity of the mobile PC. ... Posted: 2009-03-09 13:44:49 by | Network aware, How-To |
| Network Outages in Mobilized Applications [Knowledgebase] Challenge Design mobilized applications to handle network outages transparently. Although many devices include built-in connectivity, that doesn’t mean that they will always be operated in an e ... Posted: 2009-03-09 13:57:37 by | Network aware, How-To |
| Return Network Adaptor Information for a Handheld [Knowledgebase] Challenge Create a managed class to retrieve information about the network adapters installed in a handheld device using the .NET* Compact Framework. The .NET Compact Framework does not provide t ... Posted: 2009-03-10 15:02:55 by | Network aware, How-To |
| Create an ADO.NET DataSet for a Mobilized Application [Knowledgebase] Challenge Create an ADO.NET DataSet and populate it with data. ADO.NET differs from its predecessors because its DataSet object is designed primarily for disconnected operation. While retaining t ... Posted: 2008-11-24 12:33:50 by | Off-line Synchronization, How-To |
| Make Local Changes to an ADO.NET DataSet in a Mobilized Application [Knowledgebase] Challenge Update the local version of the data used in a mobilized ADO.NET application. Mobilized applications require the ability to operate on local versions of data offline that can subsequent ... Posted: 2009-03-06 08:37:36 by | Off-line Synchronization, How-To |
| Manipulate Data in an ADO.NET DataSet in a Mobilized Application [Knowledgebase] Challenge Manipulate data in an ADO.NET DataSet in order to update it or present it to the viewer. Once an application has a DataSet with one or more DataTable objects, the application must be ab ... Posted: 2009-03-09 10:07:02 by | Off-line Synchronization, How-To |
| Secure Mobilized Applications and Wireless Clients [Knowledgebase] Challenge Take simple steps to dramatically increase the security of mobilized applications and wireless clients. Security issues in wireless networking environments are well known. Nevertheless, ... Posted: 2009-03-10 15:32:16 by | Off-line Synchronization, How-To |
| Track Changes to an ADO.NET DataSet in a Mobilized Application [Knowledgebase] Challenge Create a DataSet containing only changed records for returning to the central server. This is a common requirement in a mobilized application.The insert, update, and delete changes that ... Posted: 2009-03-11 12:00:46 by | Off-line Synchronization, How-To |
| Help Secure PDAs against Misuse [Knowledgebase] Challenge Mitigate the security risks associated with PDA misuse. Unfortunately, the very attributes that make Personal Digital Assistants (PDAs) so appealing from a mobility perspective—size, ... Posted: 2009-03-03 16:08:07 by | security, How-To |
| Network Security Remedies to Secure Mobile Communications [Knowledgebase] Challenge Implement network security remedies to secure mobile communications. The rewards for using mobile data access to improve business agility and employee productivity are tremendous. Howev ... Posted: 2009-03-09 14:00:58 by | security, How-To |
| Secure Mobilized Software [Knowledgebase] Challenge Provide robust, end-to-end security in mobilized software. One particularly troubling security exposure is when a user accidentally loses his mobile device, which can often be full of c ... Posted: 2009-03-10 15:36:25 by | security, How-To |
| Secure PDAs Using Hardware Features [Knowledgebase] Challenge Secure PDAs against potential misuse using hardware features. Personal Digital Assistants (PDAs) are quickly becoming a very popular form factor for mobile computing devices. Unfortunat ... Posted: 2009-03-10 15:43:10 by | security, How-To |
| Secure PDAs Using Software Features [Knowledgebase] Challenge Secure PDAs against potential misuse using software features. Personal Digital Assistants (PDAs) are quickly becoming a very popular form factor for mobile computing devices. Unfortunat ... Posted: 2008-12-05 15:20:51 by | security, How-To |
| Mobilization Issues Associated with Terminal Emulation [Knowledgebase] Challenge Overcome traditional connectivity issues associated with terminal emulation in a mobilized environment. An advantage of terminal emulation is that it has low initial cost and is a somew ... Posted: 2009-03-09 11:50:55 by | security, How-To |
| Align and Organize Data for Better Performance [Knowledgebase] Challenge Minimize performance losses due to unaligned data. Unaligned data can be a potentially serious performance problem. It is important to remember to focus on data elements in the most CPU ... Posted: 2009-03-01 21:52:52 by | Memory cache, performance optimization, How-To |
| Align Data Structures on Cache Boundaries [Knowledgebase] Challenge Ensure that each synchronization variable is alone on a cache line. After padding synchronization structures to be the size of a cache line, as discussed in a separate item on False Sha ... Posted: 2008-11-19 14:59:56 by | Memory cache, performance optimization, How-To |
| Cache Splits with Streaming SIMD Extensions 3 Instructions [Knowledgebase] Challenge Avoid cache splits on 128-bit unaligned memory accesses with SSE3 Instructions. The Streaming SIMD Extensions (SSE) provides the MOVDQU instruction for loading memory from addresses tha ... Posted: 2009-02-13 10:06:36 by | Memory cache, performance optimization, How-To |
| Choose between Hardware and Software Prefetch on 32-Bit Intel® Architecture [Knowledgebase] Challenge Determine the effectiveness of software-controlled versus hardware-controlled data prefetch for memory optimization. The Pentium® 4 processor has two mechanisms for data prefetch: soft ... Posted: 2009-03-02 12:39:48 by | Memory cache, performance optimization, How-To |
| Create Cache-Data Blocks [Knowledgebase] Challenge Take advantage of data-cache locality with cache-data blocking. Loops with frequent iterations over large data arrays should be restructured such that the large array is subdivided into ... Posted: 2008-11-24 14:22:28 by | Memory cache, performance optimization, How-To |
| Data-Access Pattern Alignment & Contiguity on 32-Bit Intel® Architecture [Knowledgebase] Challenge Ensure alignment and contiguity of data-access patterns. The new 64-bit packed data types defined by MMX™ technology and the 128-bit packed data types for Streaming SIMD Extensions an ... Posted: 2009-03-02 13:01:23 by | Memory cache, performance optimization, How-To |
| Deswizzle Data from SoA Format to AoS [Knowledgebase] Challenge Rearrange (deswizzle) data from SoA (Structure of Arrays) format to AoS (Array of Structures) format. In the deswizzle operation, we want to arrange the data so the xxxx, yyyy, zzzz are ... Posted: 2009-03-02 13:53:38 by | Memory cache, performance optimization, How-To |
| Latency of Floating Point-to-Integer Conversions [Knowledgebase] Challenge Minimize the latency associated with converting a floating-point number to a 32-bit integer on the Intel® Pentium® 4 and Intel Xeon® processors. This is a common task, which, accordi ... Posted: 2008-12-01 16:14:04 by | Memory cache, performance optimization, How-To |
| Optimize Prefetch on 32-Bit Intel® Architecture [Knowledgebase] Challenge Optimize the use of prefetches in code for the Intel® Pentium® 4 processor and the Pentium® M processor. The performance of most applications can be considerably improved if the data ... Posted: 2009-03-09 14:56:50 by | Memory cache, performance optimization, How-To |
| Reduce the Impact of Misaligned Memory Accesses [Knowledgebase] Challenge Reduce the impact of misaligned memory accesses in an SSE2 algorithm. Misalignment of memory access is a problem commonly encountered when optimizing code with Streaming SIMD Extensions ... Posted: 2009-03-10 11:38:43 by | Memory cache, performance optimization, How-To |
| Solve Prefetch Performance Issues [Knowledgebase] Challenge Avoid performance penalties associated with excessive software prefetching. Prefetch instructions are not completely free in terms of bus cycles, machine cycles, and other resources, ev ... Posted: 2009-03-10 17:21:01 by | Memory cache, performance optimization, How-To |
| Strip Mining to Optimize Memory Use on 32-Bit Intel® Architecture [Knowledgebase] Challenge Improve memory utilization by means of strip mining. Strip mining, also known as loop sectioning, is a loop-transformation technique for enabling SIMD-encodings of loops, as well as pro ... Posted: 2009-03-10 17:36:57 by | Memory cache, performance optimization, How-To |
| Power-Aware Mobilized Windows Applications [Knowledgebase] Challenge Handle the WM_POWERBROADCAST message provided by the Windows operating system and scaling features accordingly. WM_POWERBROADCAST is a Windows message sent to applications to indicate s ... Posted: 2009-03-09 17:19:05 by | power efficiency, How-To |
| Backward Compatibility of an Application [Knowledgebase] Challenge Determine the level of IA-32 processor-architecture compatibility an application provides. Many applications today must support hardware for at least five years. This is forever in term ... Posted: 2009-03-02 09:36:22 by | Processor feature detection, How-To |
| Implement Intel® VT in the Digital Office [Knowledgebase] Challenge Make full use of Intel® Virtualization Technology in the Digital Office environment. Virtualization enhanced by Intel Virtualization Technology will allow a platform to run multiple op ... Posted: 2009-03-04 08:58:26 by | VT Virtualization, Digital Office, How-To |
| Implement on Digital Office Servers [Knowledgebase] Challenge Take advantage of Intel® Virtualization Technology at the server level in the Digital Office. Server virtualization is transforming the way leading IT organizations provision and manag ... Posted: 2009-03-04 09:10:10 by | VT Virtualization, Digital Office, How-To |
| Investigate the Intel® Virtualization Technology Ecosystem [Knowledgebase] Challenge Verify that software vendors and IT organizations will benefit from Intel® Virtualization Technology and are likely to adopt the technology. A key goal of Intel Virtualization Techno ... Posted: 2009-03-05 10:25:57 by | VT Virtualization, How-To |
| Optimize Motion Compensation on the Pentium® 4 Processor [Knowledgebase] Challenge Optimize Absolute-Difference Motion Compensation on the Pentium® 4 Processor. One important technique used in video compression is to predict movement between consecutive frames. In ma ... Posted: 2009-03-09 14:31:35 by | Develop for Core processor, Algorithm Coding, How-To |
| Optimize the AES Algorithm for the Intel® Pentium® 4 Processor [Knowledgebase] Challenge Optimize performance of the Advanced Encryption Standard (AES) algorithm for the Pentium® 4 processor. The Data Encryption Standard (DES) had served as an important cryptographic algor ... Posted: 2009-03-09 15:11:04 by | Develop for Core processor, Algorithm Coding, How-To |
| Cache Size on Pentium® M Processors [Knowledgebase] Challenge Optimize code to take full advantage of the processor's cache size, which is variable among various target machines. This optimization is important, particularly, to support high-perfor ... Posted: 2009-03-02 10:35:48 by | Memory cache, performance optimization, How-To |
| Tata-CRL Case Study [Knowledgebase] Case Study Intel® Connects Cables Computational Research Laboratories High-performance computing 02/11/08 "Almost all our reliability problems went away when we went with the Intel optical c ... Posted: 2008-12-30 13:20:45 by Preethi Raj (Intel) | High performance computing, optical cables, Computational Research Laboratories, How-To |