Intel® AVX and CPU Instructions

Real value of the CPU frequency when changed with IA32_CLOCK_MODULATION MSR

Hello,

I am working with MaRTE OS (a Hard RTOS with a Minimal RT POSIX.13 subset [marte webpage] ) and at a low level programing.

I use IA32_CLOCK_MODULATION MSR to change the CPU frecuency. It allows to me to modulate the dutycycle of the on-demand clock. The dutycycle field encoding is 3 bits. Then, I have a set of fixed dutycycle values.

Function declaration parameters - asm.

Hello,

For below HLL source code function declaration -

void apple( const State now,
Real crd[MAX_ATOMS][SPACE],
const Real v[MAX_TORS][SPACE],
const int tlist[MAX_TORS][MAX_ATOMS],
const int ntor )
--

The ICC-v11.0 assembly for above function declaration is as below -
----
# parameter 1(now): 112 + %rsp
# parameter 2(crd): %rdi
# parameter 3(v): %rsi
# parameter 4(tlist): %rdx
# parameter 5(ntor): %ecx----

Defining "Disassembly of section .plt" in C/C++ code

Hello,

Need help from assembler programmers for Inline SSE assembly programming as my understanding is very minimal.

Normally, during objdump of an executable, we have "Disassembly of section .plt" created by the loader for various operations like sin, cos, float, etc as sin@plt, cos@plt, fmod@plt respectively.

Intel Xeon 5345 & 5560 processor - FMA instructions support

Hello,

Does Intel Xeon 5345 (Clovertown) & 5560 (Nehalem) has FMA(Fused Multiply & Add) instructions support? I am not able to locate in Intel Xeon documents.

Many HPC scientific applications, it's compute algorithmhas "D = A + (BX C)" operations.

On Itanium systems, it seems FMA are supported.

With AVX, the "Intel Advance Vector Extensions Programming Reference" Chapter#6document (319433-003)speaks about FMA instructionsbeing supported.

Why such a difference of FMA support with Itanium system exist but not with Xeon 5345 & 5560 processors?

sse4.2 instructions

If I have existing c/c++ source code, do I need to modify the code before compiling with an appropriate compiler to get the benefits of the sse4.2 instructions, or will the new compilers automagically use the sse4.2 instructions for string comparisons?

Use SDE emulator for incorporating AES libraries in addition to intrinsics?

Hi, I'd like to confirm that a software developer can use the SDE emulator in order to test their code using AES-NI in multiple cases (1) using compiler intrinsics for AES-NI (2) using Microsoft CNG libraries that incorporate AES-NI (3) Using Intel IPP using AES-NI (when that version of IPP is available) (4) using openSSL libraries incorporating AES-NI. Can you confirm the SDE is useful for all these cases?

Thanks!
-Michelle

Vectorization - pragma asm interpretation

Hello,

Simply looking to interpret below things -

(a) For multiple C++ package file, when I do vectorizations (calling of pragma's) within that file within section of code, I get starting and ending asm as -
{
44d960: 55 push %rbp
44d961: 48 83 ec 50 sub $0x50,%rsp
44d965: 49 89 f0mov %rsi,%r8
44d968: 4c 63 c9movslq %ecx,%r9
...

...
44dc84: 48 83 c4 50 add $0x50,%rsp
44dc88: 5dpop %rbp
44dc89: c3retq
44dc8a: 90 nop
44dc8b: 48 8d 74 26 00 lea 0x0(%rsi),%rsi
}

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